Discussing Panel Scale Packaging at SEMI’s Northeast Forum

Discussing Panel Scale Packaging at SEMI’s Northeast Forum

SEMI did a great job at SEMICON West 2016 organizing a bursting-at-the-seams amount of technical content presented on the show floor, content that included (pleasant surprise) a full track devoted to advanced packaging topics.

Definitely not business as usual.

The distinction between where fab processes end and where packaging processes begin is blending more and more, thanks to trends like More than Moore, and SEMI is smart to stay abreast – see for example the new Heterogeneous Integration Roadmap initiative.

What caught my eye this week, and maybe yours too, was SEMI’s announcement for their 2016 Northeast Forum autumn classic in Albany, NY, where the topic this year is Panel Scale Packaging.

(Readers of this blog will remember it was Power Devices as the topic at the 2015 NE Forum.)

In the great running debate over the state of Moore’s Law, where there are now many in the industry taking the position that these are its end times, we are weighing ever more creative approaches to keeping us on the path of better-faster-cheaper in the silicon world.

We are ready for disruptive innovations. And that’s where advanced packaging makes a play.

Fan-Out Wafer Level Packaging has caught fire; as of this writing, almost everyone expects that the Apple iPhone 7, to be released in weeks, will incorporate multiple FOWLP components, as the Samsung Galaxy 7 already does.

BingoFO Wafer Level Packaging is such a good idea that maybe we should, in a nod to a combinatorial innovation way of thinking, port the technology over to substrates the size and shape of Panels as a way to continue to drive down costs.

According to SEMI, the panel approach “… offers fundamental cost advantages due to an economy of scale. Depending on panel size, a significantly large number of devices can be processed on a single substrate. In addition, the inherent inefficiencies with regards to surface area related to the round shape of reconstituted wafers can be avoided when rectangular or square panels are used.”

But is the supply chain ready? We know the Fraunhofer PLP Consortium is working on the answer to that, and we will be hearing more on the subject at the NE Forum from the panel (ha!) of experts SEMI has assembled to discuss the implications of WLP, FO-WLP, and the supply chain challenges required to scale up in panels.

The Forum, organized by SEMI’s own Margaret Kindling, who is so good leading events like this (ASMC!), includes speakers from TechSearch International, Intel, Qualcomm, Rudolph, and Corning, among others.

I’m going to put it on my list. As you should yours.

From Santa Clara, CA, thanks for reading. ~PFW