Fraunhofer IZM Panel Level Packaging Consortium Launches in Berlin

Fraunhofer IZM Panel Level Packaging Consortium Launches in Berlin

SpreeIn the bric-à-brac collection that seems to form my particular set of memories and mental associations, I have at least two old somethings crowded in a Berlin corner that I have been looking after for years, a corner to which I have now recently added something new and exciting. And work related.

The two old somethings are the writings of Christopher Isherwood (“The Berlin Stories”) and the music David Bowie made with Tony Visconti and Brian Eno in the late 1970s (The Berlin Trilogy of “Low” – “Heroes” – “Lodger”).

The something exciting, new, and work related? That would be the launch of the Fraunhofer IZM Panel Level Packaging Consortium, which was heralded by the Panel Level Packaging Symposium I attended on June 28, 2016, and which then flowed into a kick-off meeting of the Consortium’s charter members on June 29.

(I was also fortunate to have a pre-meeting on the 27th with Dr. Tanja Braun, program leader for PLP at Fraunhofer IZM, during her busy day before the main event; thank you for your kindness, Dr. Braun, for making time for me.)

The advantages of Fan-Out Wafer Level Packaging are many, which explains why FOWLP has grown so quickly to commercial prominence in what seems to be the space of just a few years, although really its history is somewhat longer than that, starting perhaps with Infineon’s eWLP process as announced in a press release they, STMicroelectronics, and STATSChipPAC jointly published in August 2008.

According to Fraunhofer IZM, the main technical advantages of FOWLP are “… the substrate-less package, low thermal resistance, improved RF performance due to shorter interconnects together with direct IC connection by thin film metallization instead of wire bonds or flip chip bumps and lower parasitic effects. … In addition, the redistribution layer can also provide embedded passives (R, L, C) as well as antenna structures using a multi-layer structure. It can be used for multi-chip packages for system-in-package (SiP) and heterogeneous integration.” (There’s our favorite term!)Alexanderplatz

Oh, and it’s cheap. (Or maybe “Cost Optimized” captures that better?)

FOWLP is currently proliferating mostly on 300mm substrates and processing equipment but, just as semiconductor device fabrication itself benefited from the economies of scale going from 4” silicon wafers back when I started in the industry to the 300mm wafers of today, maybe, if you use your imagination, even bigger substrates in fan-out packaging would be even better yet.

That would be why Fraunhofer (and others) think “for higher productivity and resulting lower cost, larger mold embedding form factors are forecast for the near future. Besides increasing wafer diameter, an alternative option would be moving to panel sizes leading to fan-out panel level packaging (FOPLP). Here, panel sizes could range from 18”x24” (a PCB manufacturing standard) to even larger sizes.”

Hence the impetus for the Fraunhofer-led Fan-Out Panel Level Packaging industry consortium, “… planned to evolve fan-out panel level packaging together with partners along the value chain as well as end-users and outsourced semiconductor assembly and test (OSAT) providers to a higher productivity level.”

“The strong drive for system integration drives strong opportunities for packaging,” said Dr. Islam Salama, Director, Substrates & Packaging Technology Pathfinding, Intel, in his keynote talk opening the Symposium.

And where is packaging going to go, Dr. Salama? It’s going to go in the direction of enabling cost-optimized heterogeneous integration so that complete system designs using fan-out technology can come to market faster, and with fewer dollars spent, than would result from the classic system-on-chip / continued semiconductor process scaling approach.

Packaging is going to go in the direction of FOPLP, because of its affordability, if / when our packaging industry comes together on standards for panel size just as our semiconductor industry did, so productively (and so long ago) on standards for silicon wafer dimensions.

Packaging is going to go in the direction of FOPLP once the equipment and materials supply chain is secure and robust across the entire panel -level landscape, and not just secure and robust for a single in-house effort.

And, foreshadowing a recurring theme at the Symposium, packaging is going to go in the direction of panel level packaging once, according to Dr. Salama, the issue of standards is resolved.

Over to you Dr. Braun, Fraunhofer IZM, the Panel Level Packaging Consortium, its dedicated members, and its dedicated efforts. In achieving the goals you’ve set for the Consortium you will be heroes … forever and ever.Berlin and Flag

What do you say?

From Santa Clara, CA, thanks for reading. ~PFW