Tessent Memory BIST (built-in self-test) allows you to test and diagnose failures in memory die and in the through-silicon-via (TSV) connections between the memory and logic die within a stacked package. This solution supports any memory stacking configurations without any change to the test infrastructure
The Tessent 3D built-in self-test (BIST) product solves the problem of accessing the TSV connections between stacked memory and logic die. We do this by integrating a BIST engine into the logic die, which then communicates to all of the stacked DRAMs through the memory interface logic. This improves 2.5D and 3D test because for the first time, BIST communicates through the memory bus rather than to individual memories, thus enabling the testing of the TSVs in addition to the memories in a stack. Our 3D BIST solution is also run-time-programmable and very adaptable. Our customers find this adaptability to be essential because no re-design is needed even as the logic die is stacked with different memories and memory configurations for different applications. In addition, we support new algorithms and standards such as IJTAG that are vendor independent and enable plug-and-play integration of memories in a 2.5D or 3D stack.
- Mentor Graphics Website
- Date this Product was Introduced to the market: 2012-08-01
- Category Product is Being Nominated for: Test and Reliability Tools/Equipment
- Technical Information on Tessant 3D IC Memory BIST