One of 60 research institutes that make up Germany’s Fraunhofer Gesellschaft, the Fraunhofer Institute for Reliability and Microintegration IZM is known worldwide for its work in the realm of microelectronic packaging and system integration. The center ASSID (which stands for All Silicon System Integration Dresden) was established as a division of Fraunhofer IZM with the core mission of developing 3D integration, interconnection and assembly technologies for the heterogeneous integration of multi-functional electronic devices into one wafer-level system-in-package (SiP). Its state-of-the art cleanroom facility houses a complete leading edge 300mm process line for through silicon via (TSV) formation, TSV post processing on the wafer front and backside, pre-assembly, 3D device stacking assembly, as well as test and in-line methodology for process control. I had the opportunity recently to visit the center in Dresden, Germany and meet with M. Juergen Wolf, who, besides being strongly engaged in Fraunhofer IZM’s wafer level system integration activities, manages and coordinates IZM-ASSID. Wolf shared some details about what distinguishes Fraunhofer IZM-ASSID from other 3D integration research programs at Fraunhofer.
First of all, to give an overall picture of the Fraunhofer approach, Wolf explained that the different divisions that make up the whole of the Fraunhofer IZM unit lend themselves to a system approach to developing solutions. “Working together with other Fraunhofer Institutes, we have different spotlights,” explained Wolf. “We have different working groups that are working together in defined project to merge all the required competences and to use synergies.” IZM-ASSID falls under the Wafer Level Integration Technologies activities header along with Wafer Level Packaging & High Density Interconnects. The other three activity areas include Materials, Reliability & Sustainable Development, Substrate Integration Technologies, and System Design. While each activity area is dedicated to its own mission, each is encouraged to work with the others to develop a holistic approach to technology development. In this way, they can achieve design, technology development, and reliability testing in systemic manner.
As the rest of the industry clamors for this very approach in the development of 3D integration technologies, Fraunhofer IZM has already seen the benefits of working together to achieve these goals. Wolf noted that from an end-use application perspective, everything is connected; multifunctional systems are needed to provide solutions. “Our vision at Fraunhofer IZM is to combine different circuits by a heterogeneous integration approach in real 3D System in Package (SiP), including ASICS, sensors, memory, transceiver devices, all together in one process as a WLP,” explained Wolf. “We are able to deal with customized prototyping, TSV interposer techniques, and via-middle, via-last for front-end. We are not just dealing with related TSV approaches, we’re also dealing with stacking from an assembly perspective as well as alternative approaches, for example, thin chip integration.”
Collaboration is the Key
Just as a collaborative culture has been developed within Fraunhofer IZM itself, so Wolf strives to foster the same culture within ASSID; investing in industrial collaborations with tool and material suppliers. “At ASSID we are focused on copper for TSV and high density redistribution layer in BEOL for interposers on both sides, Cu-TSV (via-middle process and via-last) for active circuits, and interposers completed on sophisticated leading-edge 300mm tools,” he said, adding that it’s important to understand each process as well as the line process together, rather than taking each process separately. To achieve this, the clean room is set up with actual automated process lines, rather than individual process stations, that focus on each process separately. As the ultimate goal is qualified prototyping as well as low-volume manufacturing of these 3D WLP, Wolfs team selected equipment that is compatible with industrial manufacturing, not just R&D level tools. They have also established close cooperation with equipment manufacturers and material suppliers. Additionally, he stressed that the work is not only focused on TSV/RDL processes, but also on all the assembly equipment. “We can run from wafer level process to assembly, which is pretty important for developing design rules and materials selection,” He explained. “On the roadmap to deal with cost of ownership for HVM, we can look at cost from technology perspective, and want to develop cost-effective approaches.”
To date, ASSID collaborative partnerships include e.g. Applied Materials, Oerlikon Systems, SPTS, Altatech, Atotech, EV Group, DISCO, SUSS Microtec, and Panasonic. Each collaboration focuses on developing specific processes in the overall process flow. Work on deep reactive ion etching (DRIE), sputtering, and chemical mechanical planarization (CMP) is being done with Applied Materials. Sputtering for high aspect ratio TSV is also a focus of the collaboration with Oerlikon Systems. With SPTS, work is focused on DRIE as well as chemical vapor deposition (CVD). Materials development for plating is being done with Atotech. When it comes to temporary bond and debond, as well as permanent wafer-to-wafer bonding, ASSID is in collaboration with EV Group. They are working with DISCO to develop backside thinning and dicing processes, and SUSS MicroTec is the partner-of-choice for photolithography processes. Final assembly processes such as die-to-die (D2D), die-to-wafer (D2W), is being done with Panasonic.
Wolf explained that although there may appear to be overlap with some of the collaborations, it’s because some tools are specialized for a specific process window. For example, there is a different focus with developing TSV formation processes on active circuits versus interposers. Or with metallization, there are different targets for different dimensions. In etch, for standard processes used for low volume applications, they are working with Applied Materials. For high aspect ratio etching for specific applications, development work is being done with SPTS. “We want to have the freedom to develop specific processes on selected equipment that is well suited to different requirements,” noted Wolf. “When it comes to TSV processes in wafer fabs, we have Applied Materials’ tool. In the backend, we have Oerlikon. Additionally, we do not do specific development for one supplier or one customer. We have an open platform.” He also explained that when dealing with process transfer to the customer, it is important to be flexible and go with the equipment that is also suited for and accepted in foundries and OSATS.
Focus on Interposers
When it comes to all-silicon heterogeneous integration, Fraunhofer IZM ASSID has many ongoing activities exploring interposers as a key enabler including silicon interposer with Cu-TSV, multi-layer Cu redistribution layer, embedded circuits and IPDs, optical interconnects, cooling and flip chip bonded circuit devices but also alternative approaches e.g. glass interposers.
Activities to integrate TSVs into a high performance system are very complicated, and it is more practical to have separate technologies integrated using interposers. As such, there are several generations of interposers on Fraunhofer’s roadmap, beginning with the first generation that incorporates standard RDL and with 20 µm diameter TSVs. The current generation of interposers features high-density TSVs with more than 10K TSVs/cm2 and TSV diameter less than 10µm. The third-generation of interposers will involve TSV structures, electrical optical interconnects targeting high speed and RF applications. Lastly, Wolf talked about a high-performance 4th generation interposer targeted for high performance server applications, integrating stacked multicore processors and memory in different configurations and integrated cooling. “In the next 2 or 3 years, interposers will have much more power to explore and drive 3D integration than ever expected,” noted Wolf. “Generation 4 will be like an IC embedded in the silicon. This is a very important part of the work being done here at Fraunhofer IZM-ASSID.”
As the semiconductor industry is coming to the conclusion that a holistic approach to developing 3D integration technologies is the best road to commercialization; this has been the focus of Fraunhofer IZMs center ASSID from its inception. In addition to developing a reliable and cost effective wafer level packaging process flow from TSV formation through to final assembly of 3D devices on 300mm wafers, Fraunhofer IZM ASSID is committed to working towards standardization of these processes that will be required to enable 3D heterogeneous integration to provide service for prototyping, low-volume manufacturing and process transfer.