TSMC Announces SoC Design in the Cloud at the OIP 2018 Ecosystem Forum

TSMC Announces SoC Design in the Cloud at the OIP 2018 Ecosystem Forum

As I prepared to attend TSMC’s OIP 2018 Forum on October 3, 2018 two emails from TSMC caught my attention. They conveyed the news that TSMC just lowered the entry barrier for SoC design significantly by announcing the OIP Cloud Alliance. This is the latest addition to their four Open Innovation Platform Alliances for EDA, IP, Design Services and Value Chain Aggregators.

Having promoted Barcelona Design’s industry-first cloud-based analog circuit sizing tools – more or less successfully, almost 20 years ago – I couldn’t wait to learn more about TSMC’s OIP Cloud Alliance. The inaugural Alliance members Cadence and Synopsys will storefront their capabilities for TSMC’s advanced technologies on Amazon’s Web Services (AWS) and Microsoft’s Azure cloud infrastructures.

Based on the keynotes, discussions with cloud experts at the forum and with knowledgeable friends afterward, I am convinced that designing in the cloud is now user-friendly, safe, reliable and economical.

TSMC’s Cliff HouBookend Highlights

Bookends

For me the highlights of this forum were like a pair of bookends: TSMC’s Cliff Hou was the first presenter and outlined the current capabilities of TSMC’s process technologies and design support. The last presentation of my day was by Thomas Wong, Director, Business Development, Design IP Group at Cadence. He managed to give within his 30 minutes an excellent mini-tutorial about semiconductor roles and responsibilities in automotive applications.

Cliff Hou, recently promoted to VP of R&D at TSMC, gave an impressive overview and fully endorsed TSMC’s cooperation with the four OIP Cloud partners mentioned above. He emphasized that the cloud can add CPU power to in-house compute farms and/or minimize start-up and expansion capital expenditures (CapEx).

Advanced Node Progress

Then he talked about the availability of TSMC’s advanced technology platforms and EDA support.  5nm node technology (N5) is ready for design starts. PDK version 0.5 and a broad range of design tools are certified. Many 7nm node (N7) designs are in progress and all required EDA tools are fully validated.

For N7+, which offers 1.2x the density of N7, only the OTP capability is still under development.  16 FFC in TSMC’s automotive design platform is now in production. TSMC will complete N7 in 1Q/2019, for very compute intensive automotive applications.

System-level Solutions

To solve system-level integration challenges, TSMC offers a wide range of high-density packaging platforms. Hou emphasized that interposers in CoWoS designs can now be up to 1.75 x and in 2019 will be 2 x reticle size. TSMC’s InFO platforms, used in iPhones X and Xs, now include InFO_oS (on substrate, up to 65 x 65 mm) and InFO_MS (memory-on-substrate) for combining logic with HBMs. Last, but not least, Hou explained the SOIC platform, which will allow vertical stacking of active dies, and offer tens of thousands of vertical interconnects, at pitches of 10 µm by early 2019.

Microsoft’s Kushagra Vaid

Cloud Solutions

Microsoft’s Kushagra Vaid, GM and Distinguished Engineer, Azure Hardware Infrastructure, at Microsoft Corp. was the second keynoter. He conveyed a lot of energy and a strong commitment to supporting IC design in the cloud and emphasized that Azure’s cloud services, available 24x7x365, can help to reduce IC development cost, IT infrastructure support and CapEx requirements.  Especially the backend design steps’ high compute and memory requirements can benefit significantly from the cloud. In addition, by deploying AI/ML algorithms, he says the cloud will further optimize Place & Route, Power Mgmt and other design steps.

With two brief movies, Cadence’s Lip-Bu Tan and Synopsys’ Deirdre Hanford confirmed their companies’ support for TSMC’s OIP Cloud Alliance.

Automotive Solutions

After the keynotes and a short coffee break, OIP Alliance Partners presented their capabilities and recent accomplishments in three tracks: EDA, IP, and EDA/ IP/ Services. I focused on automotive-related presentations. Here are quick summaries:

TSMC’s Tom Quan added a lot of automotive-specific details to Cliff Hou’s morning presentation. He emphasized that quality, reliability and functional safety are paramount for success in this segment and listed device aging, BTI, EM, HCI and TDDB as main challenges for automotive IC designers. He praised Mentor’s PERC as a very useful design tool in this context. Quan of course talked about the 26262 standard as a must meet and listed several other standards that guide designers.

Speakers from TI and Cadence jointly delivered another automotive-focused message. They added considering non-conductive stress (NCS) effects, that occur especially in thermal interface materials (TIM), as important too.

In addition, they reminded the audience that automotive reliability needs to be also guaranteed at – 40°C operating temperature.

Mentor’s John Ferguson presented Calibre 3D Stack and Expedition Substrate Integrator as the best-in-class flow for multi-die integration and high-reliability requirements.

SoftMEMS’ Mary Ann Maher has been focused on promoting the benefits of MEMS and sensors for many years. She added hermiticity of the package as another design challenge and asked for better IC and MEMS co-design tools.

The day’s last presentation, delivered by Cadence’ Thomas Wong, was the OIP Forum’s second highlight for me. He gave a 30-minute tutorial for automotive IC designers, explained automotive market trends and growth opportunities. He put the many automotive standards as well as a broad range of electronic functions, that are and will be needed for autonomous driving (slide 1), into context.

Slide 1: Courtesy of Thomas Wong, Director, Business Development, Design IP Group at Cadence

Realizing that the audience was just about to drown in the automotive alphabet soup, he even presented a “cheat-sheet” (slide 2) to wade through the maze of automotive acronyms.

Slide 2: Courtesy of Thomas Wong, Director, Business Development, Design IP Group at Cadence

Strategic Partnerships

During lunch and the short networking breaks, I had plenty of opportunities to discuss how TSMC’s individual OIP Alliance partners complement TSMC’s approach for manufacturing wafers and advanced packages. Since 1997, when I started to partner with TSMC on behalf of ViewLogic and later Synopsys, to develop reference flows #1 and #2 and initial PDK pieces, TSMC has focused on finding partners to complement these strengths. Encouraging and enabling their customers to move SOC design to the cloud is another strategy to win customers. ~ Herb