Heterogeneous Integration Versus Dimensional Scaling: One Year In (Part 1)

Heterogeneous Integration Versus Dimensional Scaling: One Year In (Part 1)

Heterogeneous Integration Versus Dimensional Scaling; One Year In (Part 2)At SEMICON West 2016, the big story was the end of the ITRS Roadmap for dimensional scaling according to Moore’s Law and the birth of the Heterogeneous Integration Roadmap (HIR). There were many reasons for this: the cost of continued scaling vs. the reduced performance benefits, the advantages of being able to heterogeneously integrate disparate technologies and different nodes in one device using advanced packaging; and new market drivers like the internet of things (IoT), virtual reality (VR), augmented reality (AR), artificial intelligence, and automotive electronics. So last week at SEMICON West 2017, I thought it would be interesting to take a look one year in to see how this shift in focus is impacting organizations on both ends of the line, so I asked the experts in both camps. This two-part series looks at the dimensional scaling vs. heterogeneous integration landscape.

 Scaling, not Moore’s Law, will continue
Talk to anyone at imec, CEA-Leti, and companies in the dimensional scaling world and they will tell you that scaling is far from dead. However, they all readily admit that only a handful of companies will be able to afford to implement it. Additionally, while scaling may continue, it won’t be according to Moore’s Law, which called for the doubling of transistors on a chip every 18-24 months at a reduced cost. Rather, it will require new structures, new designs, new materials, and advanced packaging technologies.

“Nothing is black and white. Scaling is continuing, but something has to be added on top,” noted imec’s An Steegan. That “something” will involve heterogeneous integration. Steegan explained that scaling used to provide the desired results on its own, but now continuing down that same path is in question. This, she says, is where true system scaling (aka functional scaling) comes in. It requires a combination of smarter circuit design, scaling at the package level, and thinking beyond just the transistor to the entire chip.

One reason for the shift away from Moore’s Law to what’s become known as “More than Moore” is the question of usage, explained Marie-Noëlle Semeria, Director, CEA Leti. Previously, the semiconductor industry was technology driven, as new capabilities were being developed. “In previous years, we (Leti) just followed Moore’s Law and the worldwide agenda. There was no question about usage,” she explained. “Now we think about the function and usage we want to have first, and develop technology accordingly.” In Europe especially, there has been a shift to application-driven development. As a result, Semaria says the focus at CEA-Leti is now on diversification.

However, according to Luc Van den hov, Director, imec, massive increases in data usage means there is still a need for high compute power that only comes from advanced node technologies. While these advancements have been slowed because of the unavailability of EUV lithography over the past 10 years, the technology is now mature. “Many companies have committed to using EUV lithography from the 7nm node on, with a roadmap extending to 3nm,” he said. “We are working hard with the supply chain on EUV elements to make sure this roadmap happens.”

While dimensional scaling may well continue to future nodes, the reduction in cost per transistor will not. Paul Boudre, Soitec, said the company used to focus on following Moore’s law until it “hit a brick wall” at 20nm. To address this, the industry first looked for new ways to build the transistor, turning to 3D FinFETs, which allowed for improved performance and increased density. But even for servers, networking, and high-end mobile devices, the cost was still too high. “At 14nm the cost per transistor went up for the first time in the history of Moore’s Law,” he noted. “For consumer applications and high volume devices, the cost cannot go up.”

This is why Soitec has invested in fully depleted silicon-on-insulator (FD-SOI) to provide cost effective, high performance, low-power solutions for IoT applications. “Samsung, ST Microelectronics, and GLOBALFOUNDRIES understand that the world and industry are changing,” noted Boudre, citing SOITEC’s manufacturing partners. “One technology cannot fit all applications. The IoT will not be enabled by FinFETs.”

Offering the foundry perspective, Tom Caulfield, GLOBALFOUNDRIES, said during his keynote address that at 22nm, the company began investigating other dimensions. What’s the next node after 7nm? “It depends. If 5nm isn’t going to achieve performance, we go directly to 3nm,” he said. “What we are doing is enabling the next steps. We have to invest in nodes where customers see value in the performance.” To do this, the foundry is engaging in all dimensions of collaboration. For example, Samsung and GLOBALFOUNDRIES took 14nm to the marketplace as competitors.

GLOBALFOUNDRIES and Samsung are among the four companies who have the resources to invest in EUV lithography, the other two being Intel and TSMC. In the past few years, all four of them have also invested in advanced wafer level packaging and 3D integration schemes to enable heterogeneous integration, and are instrumental in the heterogeneous roadmap. In Part 2 of this series, we look at how this shifting landscape is impacting suppliers to the semiconductor manufacturing industry. ~ FvT