iPhone 7: Apple Charts a Strategic Course by Selecting TSMC’s inFO Platform

iPhone 7: Apple Charts a Strategic Course by Selecting TSMC’s inFO Platform

Each year, Apple integrates more and more innovative technologies in its iPhone products. This year, with the new iPhone 7 and its A10 processor, the leading company is the first organization to bring out package-on-package (PoP) wafer-level packaging (WLP) at the consumer scale. Apple underwent a strategic change by selecting TSMC’s new integrated fan-out PoP (inFO-PoP) technology for its new A10 processor. Without a doubt, this technical choice had a strong impact on the advanced packaging industry: according to Yole Développement (Yole), fan-out activity revenues forecast should reach about US$ 2.5 billion in 2021, with 80% growth between 2015 and 2017[1].

System Plus Consulting proposes today a detailed technology analysis of Apple’s A10 processor, named TSMC Integrated Fan-Out (inFO) Package in Apple’s A10 Application Processor. Under this report, the reverse engineering and costing company provides a comprehensive understanding of the A10 manufacturing processes as well as accurate estimations of manufacturing costs and selling prices. With more than 100 relevant technical and strategic analyses per year, System Plus Consulting analysts combine their technical, marketing, reverse engineering and costing know-how in the “More than Moore” semiconductor industry, to be at the cutting edge of innovation and the most recent technologies and provide deep added-value analysis.

iPhone 7 & A10 application processor: what’s inside?

Located on the main board, A10 application processor (bottom package) and the DRAM Chip (top package) have been developed in a PoP configuration. Depending on the version, iPhone 7 or iPhone 7 Plus, the DRAM memory has different space management.

Apple’s A10 is a wafer-level package using TSMC’s packaging technology with copper pillar Through InFO Vias. This technology is replacing the well-known Through Molded Via approach. “With this new technology, Apple has made a huge break from traditional PoP packaging found in previous AP generations”, asserts Stéphane Elisabeth, RF and Advanced Packaging Cost Engineer at System Plus Consulting.

a10-cross-section_systemplus

A10 inFO package cross-section – (Source: TSMC Integrated Fan-Out (inFO) Package in Apple’s A10 Application Processor, October 2016, System Plus Consulting)

In this report, System Plus Consulting highlights Apple’s latest innovations at the packaging level. Indeed the company is offering an in-depth analysis of the packaging process including copper pillars, redistribution layer, and silicon high-density capacitor integration. The deep trench capacitor is the first integrated component developed by TSMC for high-volume consumer applications. System Plus Consulting had also available a detail report on this capacitor[2].

A detailed comparison has been performed by System Plus Consulting’s experts and especially the pros and cons of inFO technology compared to PoP packaging selected by Samsung for its Exynos 8 processor and by Qualcomm for the development of its Snapdragon 820 processor (for Samsung as well).

Thanks to the inFO process, Apple is able today to offer a very thin package on package, with a high number of I/O pads and better thermal management. According to System Plus Consulting’s report, the A10 processor is showing an impressive thickness reduction of 30% compared to traditional PoP-based systems. In addition, TSMC removed a lot of expensive manufacturing steps… “The result is a very cost-effective component that can compete with any well-known PoP” comments Stéphane Elisabeth from System Plus Consulting.

The new reverse engineering and costing report from System Plus Consulting compares costs with other chips and includes a technical comparison with the previous Apple AP, the A9…

A detailed description of this analysis is available System Plus Consulting reports section.

[1] Source : “Fan-out: Technology & Market Trends 2016” report, Yole Développement, August 2016

[2] Source : TSMC Deep Trench Capacitor report, System Plus Consulting, October 2016

Source: http://www.systemplus.fr

  • Dr. Dev Gupta

    the Vertical Interconnect Pillars in the in FO WLP are about 250 um dia at an aspect ratio of 1:1 and are at a pitch of 350 um, no denser than TMVs etc. by the OSATs and just like other peoples’ PoP unable to support multi channel buses like Wide I/O between the A10 and the LP DDR 4 chips above it. But in future they might, since at IDMs Cu pillar bumps / studs at much finer pitch and taller aspect ratio have been in HVM for processors.

    I think even TSMC might have caught up to that.