22nd TSMC Symposium Conveys Accomplishments and Looks at the Road Ahead

22nd TSMC Symposium Conveys Accomplishments and Looks at the Road Ahead

Earlier this week I had the opportunity to attend this year’s TSMC Symposium. Just like in many previous years, TSMC had a lot of progress to report and demonstrated that they have a clear vision of the road ahead.

As I expressed in previous years’ blogs, I started to get to know TSMC as a formidable competitor when I was marketing ASIC solutions at VLSI Technology. TSMC led the transition from the IDM to the foundry & fabless business model in the 1980s, put enormous pressure on IDMs and motivated me to leave VLSI. I joined Viewlogic, then Synopsys, and changed my colors from a TSMC competitor to a supporter of this rapidly growing company. We developed, jointly with Dr. Cliff Hou, TSMC Reference Flows #1 and 2 in 1998 and ‘99, and enabled foundry customers to design ICs with up to 1 Million gates, using the then current releases of Design CompilerTM and PrimeTimeTM.  From today’s perspective these humble beginnings may look insignificant, but combined with TSMC’s excellent execution, wafer manufacturing expertise, many additional partners and their visionary, focused strategies, TSMC has now earned 3rd place among the top 20 semiconductor vendors in 2015.

After looking way back, let’s mention some of the TSMC North America current accomplishments Rick Cassidy, Sr. VP and President TSMC North America, listed in his introduction. He thanked all his customers, then presented impressive numbers: In 2015, TSMC manufactured  5.3 million 12” equivalent wafers for the 5319 different products it delivered to its North American customers. He highlighted the importance of TSMC’s Open Innovation Platform (OIP) with 100s of partners in EDA, IP and services to give customers immediate access to TSMC’s latest process technologies. Cassidy highlighted that 16FFC started volume production this quarter (1Q16), the 10 nm node has a number of tape-outs in progress and TSMC is finalizing two 7nm technologies, tuned for Mobile and High Performance Computing, for risk-starts in Q1, 2017. Cassidy also talked about TSMC’s dominant market shares in several key application areas: 90% of the GPU market, 80% of Fingerprint Sensors, 70% of Wireline and 60% of Baseband and Application Processors rely on TSMC silicon.

Like in previous years, two CEOs of important TSMC customers briefly introduced their companies and highlighted some joint accomplishments with TSMC. Tyson Tuttle from Silicon Labs talked about designing low-energy connected IoT devices and Moshe Gabrielov from Xilinx focused his presentation on the many benefits TSMC’s 28, 16 and 7nm technologies offer. As pioneer in multi-die IC design, Gabrielov also highlighted the successful integration of homogeneous and heterogeneous dies, using now TSMC’s 2nd generation CoWoS technology.

Dr. Mark Liu, TSMC’s President and Co-CEO, added his worldwide perspective to Cassidy’s introduction: TSMC has 470 active customers, adds a new one every week and serves them with 220 different technologies. 16FF+ ramped volume production in 3Q2015 and 16FFC (C for compact) started this quarter and operates at supplies down to 0.5Volts. Both use identical design rules and TSMC expects about 120 tape-outs this year for the 16nm node. Very encouraging (for my multi-die IC efforts) was Dr. Liu’s announcement that TSMC’s InFO packaging technology will ramp volume production already next quarter (2Q16), for a very well known customer. Even more remarkable is that all three major DRAM suppliers have been qualified to combine their memories with a TSMC logic chip for this, cost-effective, high volume design. Beyond this major success in a mobile application, Dr. Liu also talked about TSMC’s capabilities for the ultra-low power IoT market: 55 and 40 ULP are fully qualified, 40 ULP eFlash will be done in the second half of this year. Primarily for high voltage automotive applications, TSMC will ramp 0.18 BCD also in the second half of 2016. Image sensors, with one micron pixel size, started volume production in 4Q15. Another impressive number: TSMC’s R&D budget for 2016 is $ 2.2 Billion and doesn’t even include the R&D spending of all their Grand Alliance partners.

After a very short coffee break Dr. YJ Mii, TSMC’s VP of R&D, started his presentation with comparing TSMC’s 10 nm process – which is qualified and will ramp in the next quarter (2Q16) – with the latest 7 nm development results, starting risk production early 2017 (1Q17): 7 nm will offer 15 – 20% better performance and 35 – 40 % lower power than the 10 nm node. In addition to developing these mainstream technologies, Dr. Mii outlined ongoing developments with Germanium transistors, III-V channels on 300mm wafers, nanowires and tunneling FETs for ultra-low power applications. Also, an advanced backend for 7nm is in development. To advance lithography, TSMC is working on a self-aligned quad patterning methodology that will allow <30nm pitch on a directed self-aligned process targeting < 20 nm pitch. EUV is of course also in focus and Dr. Mii expects that one EUV exposure will produce better results than four steps immersion lithography. Dr. Mii’s R&D experts have more on their plate, such as: eFlash for 40 ULP, RRAM and eMRAM, a 3rd generation BCD to lower ON resistance, Gallium Nitride technology for microwave applications and CMOS image sensors with back-side illumination (BSI). With more of the value creation shifting to advanced packaging technologies Dr. Mii of course also talked about TSMC’s Flip Chips, offering Copper bumps with 80 micron pitch and the famous InFO PoP technology with pitches of 300µm for vias, 10µm pitch for RDL and a package size of up to 15 x 15 mm.

Dr. Cliff Hou, VP R&D / Design & Technology Platform, is focused on Design Enablement for TSMC’s OIP Platform partners and mutual customers. Accurate models of TSMC’s capabilities in up-to-date PDKs, efficient and user-friendly design flows as well as TSMC’s training and support lead both groups to tape-outs quickly and allow them to utilize new process technologies as soon as the fab is ready. The fast volume production ramp-ups on which TSMC prides itself would not be possible without Dr. Hou’s Design & Technology Platform, which enables IP partners and customers to complete and qualify designs quickly and gain enough confidence to place volume orders. Dr. Hou showed us that his team supports 11,000 IP titles today, manages 70 EDA tools in the reference flows and provides over 8,000 accurate and up-to-date tech files in 250 different Process Design Kits (PDKs). In addition, Dr. Hou’s team also works with partners to create reference designs for sub-systems to lower development cost and further accelerate customers’ time to market and profit.

JK Wang, VP of Operations / 300 mm fabs, stood between us and lunch. He managed this difficult role well. Wang briefly described TSMC’s many fabs from 12 inch down to 6 inch and emphasized TSMC’s commitment to not only provide wafers, but also to offer back-end (assembly and test) capabilities. He outlined the plans for Fab 10 in Nanjing, China (groundbreaking mid 2016) and described the ongoing fab capacity expansions for 16 nm. Wang also demonstrated TSMC’s commitment to ready significant capacity for the 10 and 7nm nodes and for the wide array of TSMC’s specialty technologies. Somewhat surprising to me, Wang also talked extensively about TSMC’s commitment to minimize waste. He described how TSMC recycles 90% of the water needed and talked about other efforts to keep the environment green. It’s great to see a large corporation exerting leadership also in this area.

After lunch and some networking time with exhibitors, Dr. BJ Woo, VP Business Development, outlined her observations of market trends and projected growth potential for several market segments: She expects semiconductor revenue for smart phones to continue growing, but only at 8% annually until 2020. Infrastructure and high-performance computing will grow 10% per year, while emerging applications may even grow 28 % per year until 2020. Woo expects demand for much higher transmission speeds, more computing power and more bandwidth will finally allow us to overcome the “memory wall”. Better screens and graphics capabilities will also be in demand. Many more sensors will make equipment more context aware and smarter. Especially in the Automotive segment Woo sees a lot of opportunities for semiconductors to increase safety, security, fuel efficiency, reliability and comfort.

Mr. Suk Lee, Senior Director Design Infrastructure and Marketing, reminded us that TSMC’s 10nm technology is supported by the three major EDA vendors and showed us where Ansys and Atotech tools are qualified. He also showed the progress Ansys, Cadence, Mentor and Synopsys are making to support the 7nm technology. They’ll complement the PDK, scheduled to be ready in 3Q, 2016 – for 7nm risk starts in 1Q 2017. As I expected, Lee also talked about TSMC’s advanced packaging capabilities and announced a CoWoS based reference design kit with HBM2 memory cubes, to become available in the second half of 2016.

After the coffee break Mr. George Liu, Senior Director, Sensors & Display Business Development, demonstrated that TSMC is investing in technologies for IoT edge computing and other rapidly emerging market needs. High-resolution image sensors, MEMS, Power Management ICs, OLEDs and Fingerprint sensors are some of the technology developments he mentioned.

Last, but certainly not least, Dr. Marvin Liao, Senior Director Backend Technologies and Service Division, presented TSMC’s capabilities in advanced IC packaging to a full house. He expects that Integrated Fanout (InFO) packages will replace Flip Chip packaging, because InFO can offer more I/Os, tighter wiring and I/O pitches, thinner packages, better thermal characteristics and higher bandwidths. He also emphasized TSMCs “one stop shopping” capabilities: Providing logic wafers from their own fabs, DRAMs and SRAMs from partners and in-house capacity for assembly and test services. This “Turnkey Service Model” and many other TSMC capabilities mentioned above, will significantly contribute to continue following Moore’s Law for very high volume applications and also accelerate our industry’s migration to advanced packaging, multi-die ICs and system scaling.

If you want to know more about multi-die IC Design and Manufacturing, please download – at no charge – the 300+ pages eda 2 asic multi-die IC Design Guide here, join my session at EDPS in Monterey, CA, on April 21, or meet multi-die IC design and manufacturing experts, including me, at the IITC/AMC conference in San Jose’s Double Tree Hotel from May 23 to 26. I am looking forward to working with your team on multi-die ICs and system scaling!!! ~ Herb