Intercepting IC Products with a Disruptive Technology Option

Intercepting IC Products with a Disruptive Technology Option

rikoMuch has been written about the challenges that corporations face – especially established corporations – in adapting to a disruptive technology and the associated paradigm shifts. Most of the tomes on the subject focus on corporate management strategies. My intent is to discuss these challenges from a technology point of view – specifically when it comes to adopting so-called 2.5D and 3D disruptive integration technologies.

It is apparent that the technical and economic challenges faced by traditional “More-Moore” CMOS scaling are becoming increasingly difficult. It is hence believed that system-level integration will likely be derived from packaging technologies. 2.5D and 3D integration technologies – also referred to as More-than-Moore technologies – are often cited as possible candidates for the type of the packaging technologies that could offer the continuation of miniaturization. Note that implementation of these technologies in actual IC products is a disruptive change that will impact everything – from architecture down to test and supply chain management practices.

Adoption of a disruptive technology option involves complex technical, risk and cost tradeoffs. Judging from the past trends, and the years of personal experience of living in the space between leading edge process and design technologies, I believe that a disruptive technology option can displace an incumbent technology solution under one of the following three circumstances.

Type I: Incumbent Technology Runs out of Gas

A good reason for product implementation of a disruptive technology is when meeting target specifications by extending incumbent technology solutions become prohibitively difficult or expensive. When the incumbent solution hits a wall, the risks and costs associated with implementing a disruptive technology option oftentimes become palatable.

Use of 2.5D integration with Si Interposer solutions for high-end FPGAs, or GPU products, such as practiced by Xilinx and AMD, are examples of this circumstance. The concerns with feasibility, scalability and/or cost of achieving the target FPGA density using a traditional approach with a giant mono-die, must have made the challenges associated with Si interposer seem relatively attractive, in the case of Xilinx. Similarly, the power efficiency and bandwidth required by the high-end graphics processors must have made HBM 3D stacked memory and a Si Interposer seem more attractive than the use of traditional GDDRx off-chip memory solutions, in the case of AMD. In both situations, the incumbent technology was running out of gas, and the cost-performance constraints associated with the high-end market where these products competed created an opening for a disruptive technology. Kudos to Xilinx and AMD.

This type of circumstance is the most common condition for adoption of a disruptive technology option. Typically it is adopted first by the high-end products, which have the tightest performance requirements and the most generous margin headroom. And of course, once adapted by the high-end pioneers, the learning generated leads to the maturing of the disruptive technology solution cost structure, which oftentimes then trickles down into the mainstream. This was, for example, the case with C4 flip-chip bumps, and many other technologies that were a disruption to the then status-quo and will likely be the case with high-density Interposers.

Type II : System Level Value Proposition

An alternative situation is where an incumbent technology can still meet the target specs, but a disruptive technology option offers an opportunity for a better value proposition at the system level.

An example of this is the opportunity offered by the Wide/IO DRAM stacked on a baseband logic die using TSV technology (the disruptive option) vs. using LPDDRx DRAM with package-on-package (PoP) technology (the incumbent solution). The power efficiency and form factor advantages offered by the Wide/IO DRAM technology were very well publicized, and seemed attractive and well positioned, especially for mobile applications. Multiple companies competing in this space – including TI, ST, Samsung and Qualcomm – all invested engineering effort to evaluate this option.

However, Wide/IO with 3D TSV stacking has not been adopted (yet?).

We can conclude that the advantages of this disruptive technology option did not outweigh the disadvantages. (Duh!) Note, however, that this circumstance involved tradeoffs between increased costs and risks at the component level vs. benefits that could be monetized only at the system level.

Thus, the TSV technology required for 3D stacking involves CMOS process and SoC design changes that result in processor component cost that can only be equal to or larger than the traditional solution. Similarly, Wide/IO DRAM – especially for densities above 1GB – involved costs that can only be equal to or larger than those for the equivalent traditional LPDDR DRAM. In addition, 3D Wide/IO stacking involves perturbation to the well-established PoP sourcing model, which has to be perceived only as increased risks.

The form factor (in x,y and z dimensions) and power (use-case-dependent) advantages at the component level — universally perceived as goodness in the mobile sector — could however be leveraged and monetized only at the system level, potentially yielding thinner or smaller phones with better displays and/or battery life, etc.

Realizing this type of a cross-domain tradeoff requires co-design and coordination capabilities necessary for full and complete optimization at the system level — crossing corporate boundaries and transgressing normal development schedules. At this time, this is not practiced, especially within the ubiquitous distributed sourcing model involving OEMs (LG, Xiomi…), semiconductor entities (Qualcomm, Mediatek…), DRAM vendors (Micron, Hynix…), etc…

In the absence of such a holistic, system-level optimization, accompanied by a fully integrated co-design environment, we can conclude that when cost is on the side of the incumbent technology solution, it trumps the advantages offered by the disruptive technology candidate. This is especially true when the system architecture is optimized for the incumbent solution, rendering the value proposition of the disruptive option less than optimal.

Type III : Component Level Value Proposition

The third circumstance for intercepting products with a disruptive technology option is a situation where an incumbent technology can meet the target specs, but a disruptive technology option offers an opportunity for a better value proposition at the component level.

An example of this is multi-chip packaging, either to bundle existing components in a single package, or to enable breaking up a complex SoC into several smaller die. Use of advanced 2.5D and/or 3D packaging technologies can clearly enable such a solution, potentially resulting in better component level cost structure by eliminating individual packages, or by leveraging the yield of small die vs large die, or by leveraging mature technologies for functions that do not need the power-performance of a leading-edge technology, or by a combination of these. This opportunity has been — and is being — assessed by many companies, using Si, organic or glass interposers, or fan-out technology, or some mix of the various 2.5D / 3D integration options.

However, there are not many products in HVM competing in mainstream markets that leverage the 2.5D/3D technology option (yet?).

Whereas, at the concept level this opportunity may seem rather obvious — almost trivial; experience indicates that finding that ‘sweet spot’ requires very complex and detailed analyses. Achieving a lasting value proposition with a disruptive option, relative to the incumbent technology solution, mandates making the right tradeoffs from design down to manufacturing. The trade-offs and the associated analyses are complex, with knobs in Si technology space (e.g. cost, yield and yield learning for the various technology candidates), package technology space (e.g. cost vs. interconnect density vs. various form factor constraints), design space (e.g. architecture, chip floorplan, IP design), test space (e.g. cost of probe test vs yield), etc…

Realizing this type of a product intersect with a disruptive technology option calls for coordination of multiple disciplines within the semiconductor IC product arena, and a design analyses environment that enables evaluation of many tradeoffs – aka PathFinding. In the absence of a holistic pathfinding environment, or a multidisciplinary team performing the pathfinding analyses manually, it is difficult to quantify the value proposition so that it is perceived to outweigh the risks. We can conclude that even if it seems that the cost is on the side of the disruptive technology option, it does not necessarily trump the advantages offered by the incumbent technology solution.

So does this mean that the 2.5D/3D More-than-Moore type of technologies will intersect actual IC products only if and when the traditional More-Moore solutions run out of gas? Or that the only scenario where a disruptive technology displaces an incumbent technology is when cost considerations are suspended, as is the case with high-end products and Type I intersect? Or that the only way that other types of intersects can be realized is when the co-design and/or PathFinding tools and methodologies are available as turnkey solutions? Possibly….

On the other hand, the type II intersect, where the value proposition of a disruptive technology is realized at the system level, may be an avenue that is attractive to the few fully vertically integrated entities who do control all or most of the system and component design knobs. Perhaps they will be forced to do so by opportunities of differentiation in highly constrained markets – such as for example the watches and other wearable applications?

Type III intersect, where the value proposition of disruptive technology is realized at the component level is a lower hanging fruit that could be realized by many semiconductor companies who do own most of the knobs that affect the IC component cost. Perhaps they will be forced to do so by opportunities of differentiation when trying to break into new markets – such as for example the adjacent markets that many established entities pursue when their traditional markets are saturated. ~ R. Radojcic

  • Riko, this is a great analysis of some of the technology tradeoffs being considered today in advanced packaging, but your use of the words “disruptive” and “sustaining” are quite different from that of the business school professor who put them in the forefront of our lexicon…

    As Andy Grove is said to have recognized when Christensen was giving his presentation at Intel, it is really not about technology, but about markets. Those who want to bring new technologies into the mainstream have to see if they support (sustain) the existing products (as seen by the customers). Otherwise they have to find new customers who value the very features which may be seen as disadvantages by the existing market.

    From my perspective, that opportunity is presented most clearly by wearable applications (both consumer and medical) where the margins are relatively low and performance is far from state of the art, but form factor and power consumption are critical “go/no go” issues. The ultimate in miniaturization will be worth something to those markets.

  • Riko R

    Thank you. Good point re ‘disruptive definition’. I was using the term to collectively describe 2.5D and 3D type of technologies – mostly because I believe that successful deployment of these technologies requires substantial changes at the chip architecture and/or design level, i.e. these technologies cannot just be retrofitted to existing designs. IMHO. Hence ‘disruptive’.
    Agreed re discrimination between difference in disruptive impact on technology vs on markets, and the opportunity with the wearables… Thanks

    RR