You might think this is crazy but bear with me for 421 words.

Early in my career, I worked at an IDM as a product engineer and manager over IC products. ‘We’ were responsible for the overall product cost, maintaining yields (including speed binning) as well as improving yields. This was long before the SoC/ASIC disaggregation. This IDM was vertically integrated and had its own mask production, fabrication, assembly, test and branding operations. So our job was to watch over the entire process and ensure planned yields and costs were achievable to protect our gross margins.

Understanding yields and their impact on costs was learned on a daily basis. Slight changes in Bipolar or CMOS processes or test programs would quickly be seen later in the manufacturing process: some helped reduce costs while others unfortunately raised them. One of the key tenets was to stop bad or even questionable material as early in the flow as possible. This prevented costly operations (equipment time, additional material and labor costs) from being wasted on units that had little chance to work. So the key was to characterize any units going through a process point to determine which parameters’ specifications predicted a unit’s future functionality. For parameters that did not have much input, you could loosen the spec or not even test it. But for the many parameters that affected the end functionality, careful testing was required to determine additional tools and/or guard bands that would screen out as much bad material as possible. Since a unit’s value is highest at the end of a manufacturing line, much of the characterization was performed ‘upstream’, at the very beginning, to weed out questionable material¹, fix out of spec manufacturing equipment and identify marginal designs.

Wafer probe was the key upstream operation for controlling the downstream yields and therefore costs. Tighter screen might lower probe yields but at this point, it was just the cost to manufacture the die. This made sense if you could drive up your packaged IC yield at final test where the invested material, equipment time and labor were greatest. But there was another hidden cost that we did not recognize at a product line perspective. There was a hidden opportunity cost to poor yielding products in the fabrication/assembly/test flow. The poorer yields caused more material to be started to meet customers’ purchase orders. It also tied up limited equipment and people in all areas and prevented us from manufacturing other products. This situation could induce ‘product allocations’ due to resources shortages rather than end market demand!

At this point, you might state: So what!?

The same constraints affect any design organization. You have limited resources (people, compute hardware and software) and time to complete complex designs. If a design ‘manufacturing’ environment does not screen out questionable implementation options early in the process, teams of people and tons of resources are tied up on an activity that will likely fail. As with the IDM situation, some costs are visible (people, HW/SW) while similarly opportunity costs are hidden. The opportunity costs are the most important to minimize: they prevent new designs from being developed that can open up new markets and new revenue streams.

How can Product Design learn from Manufacturing? By quickly eliminating inane implementation options as early as possible in your design flow/methodology. One way to augment a design flow/methodology is to add Path Finding before costly design implementation steps begins. Path Finding tools allow many test cases to be quickly constructed and accurately analyzed: objectively differentiating the viable from the inane.

As with wafer probe, Path Finding is the key upstream activity for improving downstream product design activities. By removing the inane implementations from entering the costly design implementation- and verification cycles, Path Finding addresses the visible and hidden costs in product design and speed up time to profit significantly.

1 Bill Martin, Path Finding: Who performs and When? GSA Forum June 2013 issue.

Bill Martin

Bill Martin worked at an IDM (Mostek), an ASIC company (VLSI Technology), an EDA company…

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