ECTC 2014: A Preview of 2.5D and 3D Activities

ECTC 2014: A Preview of 2.5D and 3D Activities

Each year, the agenda of Electronic Components Technologies Conference (ECTC), an international conference sponsored by the IEEE Components, Packaging, and Manufacturing Technology Society (CPMT), is jam-packed full of tutorials, keynotes, panels, technology sessions, and interactive poster sessions covering the latest developments and emerging technologies in microelectronics components and packaging. Featuring the latest in flexible electronics, silicon photonics, and wireless power transfer systems; 2.5D and 3D integration technologies makes up just part of ECTC 2014; but that’s the part this preview will focus on.

Back again this year; John Lau of ITRI will lead a professional development course (Tuesday, May 27, 1-5pm), 3D IC Packaging and 3D Si Integration, which will focus on the differences between the two, and will elaborate on the benefits of 3D Si Integration as it applies to high volume manufacturing (HVM) applications. Lau will discuss supply chains and the critical process and manufacturing steps, as well as test and liability ownerships. 3D IC packaging, which has been keeping 3D IC integration away from volume production, will be briefly mentioned first.

Alternatively, offered at the same time is a course on Thermo-electrical Co-design of 3D Chip Stacks, lead by Avram Bar-Cohen and Ankur Srivastava, University of Maryland. This course stresses the importance of “co-design” due to greater need for embedded cooling in 3D ICs. Underscored is the need for better unification of the thermal and fluidic aspects of the system into an integrated co-design environment that enables designers to estimate the impact of the cooling solutions on the electrical aspects and vice versa. Such a co-design approach is imperative for unlocking the high performance and energy efficiency of 3D ICs.

This year’s ECTC Luncheon Keynote (Wed, May 28, 12pm) will feature Peter L. Bocko, Ph.D. CTO of Corning Glass Technologies, who will explore Glass: The Art, Mythology, and Technical Agility of a Material of the Information Age. As the use of glass in semiconductor platforms, and specifically as an interposer material for 2.5D applications, has been heavily researched and debated over the years, it seems very appropriate to have Bocko, who is well respected as one of the foremost glass experts in consumer electronics, present his perspective. Bocko’s talk will focus on 3 areas: glass’ evolving role since antiquity, technologically in the immersive information environment, and culturally as a vehicle for artistic expression.

Wednesday evening, (May 28, 7-9pm) join Nancy Stoffel, of GE Research, as she moderates a panel discussion titled Packaging Influence on System Integration and Performance, featuring panelists from IBM Corporation, Cysco, Amkor and Ericsson. The system-level panelists will discuss current system-level requirements, challenges, and the roles played by component packaging an integration technologies. The supplier-side panelists will discuss how efforts to create highly-integrated systems-in-package (SiP) will address current and emerging needs. I plan to attend and ask questions directly related to the roles 2.5D interposer and 3D IC technologies will play in this.

If you’re interested in learning about alternatives to high-cost Si interposers for fine-pitch 2.5D and 3D integration, then you won’t want to miss the CPMT Seminar, Latest Advances in Organic Interposers (Thursday 8-10pm), co-chaired by Kishio Yakouchi, Fujitsu, and Venky Sundaram, Georgia Institute of Technology. Comparisons of Si, glass and organic laminates have been an ongoing topic of discussion over the past few years. Si interposers for fine-pitch applications are considered to be mainstream now, although it is the most costly option. Research is growing for glass interposers and through glass vias (TGV) due to the cost benefits and superior electrical properties. Current believe is that organic laminates reach their limits for high-density applications at 5µm L/S, and that beyond it is necessary to go to Si interposers. Panelists from IBM Japan, Ltd; Xilinx, Inc; Shinko Electric Industries, Co Ltd,; and Kyocera SLC Technologies Corp. will discuss user needs for interposers in high-performance mobile applications, and the possibility of Organic Fine-Pitch Interposers (<5µm line and space).

The sessions throughout the week focused on various aspects of 2.5D interposer and 3D IC integration are too numerous to go into detail here. To narrow your decision-making, I recommend you start with 1, 7, 13, 14, 19, 20, 25, 26, and 31. There are also 3D presentations scattered throughout the program, as well as interactive poster sessions. Chances are, you will learn something new. Additionally, don’t miss the exhibits in the Technology Corner, where 2.5D and 3D suppliers will be ready to answer questions about their latest activities in 3D integration. Hope to see you there. ~ F.v.T.