Archives July 2012 - 3D InCites

SEMICON West 3D (and more) Mash-up

Now that I’ve finished (finally) writing and posting all 3D InCites original content, I thought I’d take a look around and see what some of my blogger/journalist colleagues had to say about SEMICON West 2012 and do that curation thing I keep talking about. SEMCON West Eye CandyOn the video front, kudos to ChipEstimate TV, who managed to add some flash and pizazz to what can be (let’s face i... »

3D R&D Update, As Told by the Experts

The R&D centers were out in full force at this year’s SEMICON West, presenting on their latest activities in all areas of 3D technologies, from 3D transistors, to 3D ICS, to full-blown 3D Systems. I was able to attend a smattering of presentations at events hosted by imec, CEA-Leti, SEMATECH and SUSS MicroTec, and fortunate to score face-to-face interviews with Ludo Deferm, of imec and Mark... »

Outside the 3D TSV Box

As much as the industry is intent on holding 3D technologies to a narrow definition, I'm compelled to remind readers that before 3D had to include a TSV interconnect to be considered a 3D technology, and before the term 2.5D had been coined, 3D packaging was already being touted as a value-add way to accomplish improved performance and form factor issues. At SEMICON West, I met with executives fro... »

An Incomplete List of 3D Solutions

We read a lot about the remaining challenges to be addressed before 3D ICs are fully commercialized. Current roadmaps are now targeting 2015 for commercialization of 3D ICs, while 2.5D gets the ball rolling towards the end of 2012, beginning of 2013. Reports from Xilinx indicate they are shipping 2.5D products in thousands, and it's next-generation 3D product in the hundreds (they've added a trans... »

Tips on Modeling Warpage for 3D ICs

This week’s webinar on chip stack assembly simulation, presented by Kamal Karimanal of Cielution offered some useful information on how modeling can be used to minimize warpage in 3D stacking. In 3D stacking, versus traditional flip chip processes, thickness of RDL layers in comparison with the thinned die or wafer can lead to warpage issues. The reason this is important is because through si... »

Musings From SEMICON West 2012

Tish LeBlanc, from TI: "How's your SEMICON West going? Me: "I was just trying to put it into words." It's Thursday, and another SEMICON West (my seventh) is winding down, and its the first time I've found time to write since Monday evening. As always, it's been a whirlwind of sessions, editorial appointments, networking events, and for the first time for me, video interviews. When presented with »

Industry Collaboration: Everybody’s Talking About It

Well, I missed half of Monday's activities at SEMICON West thanks to a two hour flight delay. I skidded into the imec ITF just in time to catch the tail end of Luc Van den hove's technology overview.  He was saying that the requirements of smart devices communicating with the Cloud requires development of ultra-high technology servers, which along with smarter devices,  will require 3D-enabled ... »

Design and Test Solutions are Trending in 3D ICs

These days, as I troll the pages of the Internet in search of juicy tidbits of 3D IC news and information, I’ve realized that with the exception of that pesky issue with thin wafer handling, focus has moved away from novel manufacturing processes, and turned its magnifying glass onto the world of design, test, reliability, signal and power integrity, ESD challenges, and so forth. This is proving »

Wanted: Industrial Partners for Novel TSV Development

A few months ago, Andreas Fischer, of the Microsystem Technology Laboratory School of Electrical Engineering Royal Institute of Technology, Stockholm, Sweden, contacted me to tell me about a novel process for filling TSVs that he had been working on from first proof of concept in August 2008, as part of his doctoral work, and with strategic support provided by KTH Innovaton.  The process veers c... »

The Flip Side of the Glass Interposer Coin

We’ve been hearing and reading a lot about work being done at Georgia Tech’s PRC in developing glass interposer technologies as a low-cost alternative to silicon in 2.D and 3D applications. Mostly, it’s the cost benefits that are being touted. However, what sort of journalist would I be if I didn’t also report on the flip side of this technology? Today I spoke with Madhavan Swaminathan, w... »

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