Industry Collaboration: Everybody’s Talking About It

Well, I missed half of Monday’s activities at SEMICON West thanks to a two hour flight delay. I skidded into the imec ITF just in time to catch the tail end of Luc Van den hove’s technology overview.  He was saying that the requirements of smart devices communicating with the Cloud requires development of ultra-high technology servers, which along with smarter devices,  will require 3D-enabled scaling to achieve desired functionality. 

He went on to discuss the changing landscape of the semiconductor ecosystem. Calling the current captive business model unaffordable and outdated, Van den hove talked about another type of 3D; a three dimensional approach to collaboration between R&D, academia and industrial partners to bridge the gap.

This sentiment was echoed by Mike Splinter, CEO and Chairman of the Board of Applied Materials, in his presentation. Splinter talked about  how we are at the beginning of the  Age of Mobility, where we are coming to rely on the internet of things as an integral part of daily life. We are coming down on the “other side of Moore’s Law” and as an industry we are facing such issues as how to improve and accelerate efficiency of our R&D and manufacturing as well. While keeping pace with Moore’s Law, we also  have to simultaneously address the increasing complexity of our devices, and also realize the transition to 450mm wafer sizes. We have to find models and prioritize, eliminate waste and find efficiencies. As one solution, he mentioned consolidation in  the equipment space, which is what we’ve seen happening over the past year.  

Close collaboration between R&D, academia and manufacturing has become a recurring theme over the past few months in the 3D space, but the concept extends beyond that to include integration of enabling technologies for further scaling. As I listened to technology presentations outside my general area, such as traditional CMOS scaling, FinFETS, double patterning lithography, photonics, and a concept referred to as “beyond CMOS scaling” because it involves materials besides Si; I realized a subtle difference in the way imec references these different technologies as they relate to each other. Rather than viewing them as competing technologies, lobbying for the same funding resource, they treat them as complementary technologies that collectively will solve future technology challenges. So from the imec perspective, 3D is not an alternative to scaling, it’s become a critical tool to continue scaling further. As a result, the “super chip” envisioned by imec researchers will leverage all the work they do and will comprise 3D memories, photonics, double patterning, and more.

SEMICON West activities will be in full swing tomorrow, This year’s tagline is “The Power of {X}. I’m thinking if x=Collaboration, the overriding theme of this year’s event will likely by “The Power of {Collaboraton}. ~F.v.T