Whether you’re a believer or a skeptic, there’s no arguing that discussions on 3D continue to draw a crowd. For the second year running, the room was bursting at the seams at the IMAPS Device Packaging Conference 3D Panel discussion. Literally. They even took down the wall to expand the room.

The panel was overflowing as well. Jan Vardaman moderated a gregarious group of industry vets with her signature dry wit. (In this industry especially, it’s always nice to see a woman taking charge once in a while, don’t you think?) There was the SEMI Award winning Bob Patti of Tezzaron Semiconductor; the elusive Paul Siblerud of EMC3D, and – as Jan put it – the soon to be assimilated SEMITOOL (by Applied Materials); Matt Nowack of Qualcomm represented the end users. His slide deck guided the discussion around Qualcomm’s roadmap for what they call TSS (through silicon stacking). We were treated to a rare appearance from the test community, Michael Wright, former president and CEO, Advanced Inquiry Systems Inc (AISI). Ron Huemoeller, Amkor’s VP of 3D interconnect technology, spoke on behalf of the OSAT community, and of course, 3D panelist-at-large, Phil Garrou, wearing his IMAPS Fellow hat for this occasion.


Is test a barrier to 3D TSV adoption?

Vardaman started things off where last year’s panel discussion ended – with a question about test. I was excited: hopefully we’d be learning something new. In answer to her question, Wright responded that what’s needed is in-line testing of TSVs that makes contact without damaging wafers, and then gave a nice demonstration of AISI’s tester interface system.

The test discussion went on for quite a while, with lots of speculative discussion, repeats of the same concerns from last year, some solid ideas, but no magical solutions. Here’s what I got from it:

Nowack said test can be manageable if you design the system with design-for-test (DfT) from the start. Known good die (KDG) is essential, but testability has to be a constraint when you do tier to tier partitioning in order to use conventional techniques.

Garrou suggested taking a logical look at the issue. He said if you believe the numbers, there are 15 lines going in to do this “Does it make logical sense that companies would pour money if there was no way to test stacks?” he said. “Large companies are not doing this blind, assuming a test solution will miraculously appear.” In other words, it’s part of the secret sauce. Makes sense to me.

Huemoeller said Amkor has test on the roadmap, with potential solutions based on geometries already in production. He added that they are not ready to probe copper, but are looking at alternative technologies.

Patti reiterated last year’s position in favor of self test and repair, which Tezzaron already implements in its designs. The primary reason being that making contact with delicate TSV structures will damage them. He also offered a refreshing dose of candor and reality saying point blank, test will be driven by cost. It’s too expensive to test layer by layer. It costs less to test the final assembly and if it fails, throw it away. Decisions will ultimately be based on yield value. If putting together parts that have 50% yield and cost $100 to manufacture, you’ll find a way to test them along the way. If the parts cost a few cents to manufacture, it’s cheaper to just throw away the ones that fail.

Role of wafer fab and OSATS
Based on the panel responses, there seem to be more firm positions on this question than last year, indicating some real movement as foundries and OSATS claim their territory. Huemoeller explained that based on customer trending the different roles are emerging. It looks like processes through via finishing will be the roll of the foundry, while OSAT will pick up from backside finishing through assembly and final test.

Garrou noted that in the past year, some of the options have been narrowed down and that’s helped things along. Via middle (the new via first) will come from the foundry, via last will come out of the OSAT. There was a general consensus among the panel on this, with the exception of silicon interposers, noted Huemoeller. That would be a foundry project.

Nowack said the supply chain handoff will ultimately dictated by who has made the investment to understand a particular technology and invest in the equipment.

At this point in the discussion, Vardaman put Siblerud on the hot seat – asking if the EMC3D consortium’s cost model targets include things like singulation. He explained it includes the wafer processing for creating TSV structures in the front end. The rest is done in the back end. He also told me earlier that the targets assumed the kinks had been worked out of the processes.

Silicon Interposer Debate
Moving right along, the discussion segued from there to a discussion about silicon interposers. Overall, the panelists agreed that silicon interposers serve as a bridge technology to 3D ICs.

Nowack noted cost as a key inhibitor to silicon interposers. He doesn’t consider them to be a replacement for TSS. Quacomm has strong interest in via middle TSS without interposers, however he noted, “Interposers could be a very good pipe cleaner for the supply chain.”

Silicon interposer as a temporary solution is what keeps Amkor from investing in a line, explained Huemoeller. “It doesn’t make sense to do it if the market is temporary,” he noted.

“Interposers are a temporary band-aid until you can do something better. It doesn’t have value in and of itself.” said Patti. However, he added that it depends on what you want to do with it, power distribution, for example. Interposers with integrated passives may have enough value to justify investment.

Siblerud suggested that the lack of standards make interposers the only real option for IDMs, who like to control the whole architecture. Lots of IDMS are working with interposers, he said. They’re also a good solution for heat dissipation.

Standards, design, etc
Mentions of standards was sprinkled in throughout the discussion. Garrou expressed his ire around JEDEC’s refusal to share who authors standards, and that transparency was needed for standards to be qualified. Nowack said Qualcomm has expressed a need standards in area such as thin wafer handling, debond processes, design rules, criteria for reliability, etc.

Some of the most notable progress since last year has been in the design realm. Nowack expressed confidence that design/EDA challenges can be managed. Qualcomm’s TSS methodology roadmap calls for a 2 phase approach. In phase 1, chips are designed one at a time using enhanced 2D design tools. (2.5D) Phase 2 involves true 3D design, co-design across multiple die and automated full-stack design in the next year or two.

Last year, panelists noted that the big design houses wouldn’t get going with tools until their customers started clamoring for them. That time has come. According to Nowack, Synopsys plans to have a full suite of 3D design tools available by 2012.

All in all, the panel was fairly confident that TSV market adoption is closer than some might expect. For those of you who attended, as well as those who didn’t, I’d be interested in your input on these same topics. I invite you to post your comments here — F.v.T

Francoise von Trapp

They call me the “Queen of 3D” because I have been following the course of…

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