Designers add their voice to the 3D integration journey

After being immersed in the 3D design world over the past few weeks I realized a few fundamental differences between design engineers and process engineers. Now you, as a reader, may be thinking that I’m pointing out the obvious. But the point is, as 3D processes – and particularly through silicon vias (TSV) – attract the attention of the design community, different perspectives surface.

It’s no secret that process engineers and design engineers look at things quite differently. Process engineers want to know, can it be done? They have to be concerned with manufacturing cost, yield, reliability, increased functionality, etc. Once proof of concept has been established and prototypes have been taped out, design engineers step in and decide the benefits these new technologies have from a design perspective. Will the design process be simplified? Does it allow for better use of substrate real estate? Further, design engineers also can look at a proof of concept and ask, what else can we use this for?

To paraphrase Bill Martin, of E-System Design, from a design perspective, TSVs offer the opportunity to allow each IP to be designed in processes tuned for its needs rather than relying on the same, perhaps overly complex, costly process. TSV designs can be tailored to suit niche fab processes, and “enable faster, cheaper, platform based designs.” So while per wafer manufacturing costs are still too high to be viable, the end-result design savings also need to be considered.

Another insight of the design community is that as a device rather than a ‘wire’, TSVs have other valuable applications. As Madhavan Swaminathan, also of E-System Design, explained to me, TSVs provide options for solving other 3D integration issues such as power delivery, clock distribution, managing hotspots etc. He talked about work being done at Georgia Tech and other places to develop technologies whereby TSVs can be made hollow to pump fluids for thermal management, or in photonics applications, where suitable cladding allows TSVs to guide light.

Looking at things from the design perspective also helps explain why design tools are among the last hurdles to overcome. As Leti’s Ahmed Jerraya explained in last week’s discussion, proof of concept and prototype 3D chips and packages can be designed using ad hoc 2D tools, but to design for production, specific 3D design tools are necessary. As such, Leti has formed a common lab agreement with R3 Logic, a 3D specific design tool start-up, in order to work with R3 Logic’s floorplanning tool for Leti’s 3D designs. Part of the hold-up is that there are so many process options designers still lack the experience to select the right ones for the job. However, Jerraya says this will rectify itself when EDA tools are available.

What’s important about all of this is that it’s clear that the design community is fully engaged. From risk taking start-ups to large design houses, work is underway. It won’t be long now. – F.v.T.