3D InCites’ Guide to Navigating theThird Dimension at SEMICON West

There’s no doubt about it, the 3D technology related workshops, lectures, and presentations happening at and around SEMICON West this year are plentiful and varied. There’s something for everyone: 3D metrology, 3D interconnect and standards development; 3D IC co-design, 3D bonding and thin wafer handling, 3D test solutions, commercialization of TSV and cost of ownership, supply chain considerations, etc. Trying to fit it all in will require some careful strategizing, because many of the events run concurrently. To make it easier, we’ve provided links to agendas, and even pdfs when available right here. So you may want to bookmark this page for future reference.

Some of the workshops are all day events, so you’re either going to have to sacrifice one for the other, or register for all of them, and cherry-pick from the presentations that are interesting to you. Monday, July 12, is an easy day, if you’re already in town for ASMC. The 8:30am keynote by Matt Nowak, of Qualcomm will discuss “High Density 3D Through Silicon Stacking – Manufacturing Readiness and Challenges”, while later that day (4:40), you can catch Jim Walker’s perspective at the SEMI/Gartner Market Symposium when he addresses “3D: Adaptable Manufacturing for the Next Decade”. Both events are at the Marriott Marquis on Fourth St., so you don’t even have to leave the building to make both.

On Tuesday, July 13, you’re going to have some decisions to make. SEMATECH’s got an all-day workshop on the topic of Stress Management for 3D ICs using TSVs at the Grand Hyatt from 9-5pm. This workshop is intended for IC designers and manufacturers; TSV technology developers; electronic design automation (EDA) experts; and semiconductor assembly and test service providers, so if you fall into one of these categories you might want to check it out. See who’s speaking here.

Alternatively on Tuesday from 10:30-12:30 at the North Hall TechXpot , is “Bridging the Gap”, which will address how 3D Packaging and 3D IC can best be harnessed to provide mobile device products that meet the needs of the consumers and markets of the future. Speakers and panelists include Steve Bezuk, Ph.D., Qualcomm; Jan Vardaman, TechSearch; Jim Walker, Gartner (in case you missed him on Monday); Phil Garrou, Microelectronic Consultants; Rick Rice, ASE; and Albert Wu, Marvell. Find the complete agenda here.

Chip, package and system designers interested in learning more about the latest requirements for 3D TSVs as this emerging technology approaches commercialization should be sure not to miss the session in the North Hall Tech Site from 2:30-4:30 entitled 3D IC Co-design Challenges: How to Speed 3D IC Deployment.  Representatives of Mentor, Cadence, Gary Smith EDA, Atrenta, DfR, Georgia Tech, and the GSA EDA interest group will be presenting.

On the other hand, if you’re main interest lies in learning the latest in 3D bonding, thin wafer handling, as well as a look at 3D test solutions, then you’re best bet is SUSS MicroTec’s second annual 3D IC Bonding and Thin Wafer Handling Workshop, which takes place Tuesday July 13, from 2-5pm. The workshop is free, but space is limited. You can learn more and register here.

If your thing is 3D standards, than you’re wise to spend your entire Tuesday afternoon from 1-5pm in the Marriott Marquis at SEMI/SEMATECH’s 3D Interconnect Challenges and Need for Standards Workshop. In addition to technical exchange and constructive discussion and problem solving, the target is to identify one or several areas of standardization, with the final goal being to identify participants willing to provide guidance and support with the development of new standards.

Which brings us to Wednesday, July 14 and the SEMATECH Workshop on 3D Interconnect Metrology,  from 1-5 at the Marriott Marquis. The purpose of this workshop is to gain a better understanding of how new and existing wafer metrology technologies can be utilized, modified or enhanced to measure and improve 3D interconnect processes. Several 3D InCites partners are represented in the speaker line-up, including Markus Wimplinger, of EV Group, who will present a paper, Infrared Overlay Metrology of Bonded Wafers and Stacked Layers for 3D Integration at 3:40pm; and Shari Farrens, Suss MicroTec, who will present Infrared Overlay Metrology of Bonded Wafers and Stacked Layers for 3D Integration at 4:40pm.

Co-located with SEMICON West on July 14 from 8-5pm, is IMAPS Advanced Interconnect Workshop,at The Marriott Marquis, which features session on 3D interconnect from 9:30am to 12:00. Among the presenters is Bioh Kim, of EV Group who will present Advances in Wafer Bonding Enabling Vertical Integration at 10:30am. And then Thursday, July 15, as part of NCCAVS Plasma Application Group’s session at Tech Site North, Eric Pabo, EV Group, will – present Plasma Activation – an Enabling Technology for Wafer Bonding. Other than a few invitation-only events which you’ll know about if you’ve been invited, that about covers it. Please comment here and add on if anything is missing that members need to know about.

PS: Be sure to visit 3D InCites Partners at the following locations:

  • Alchimer  #1811 South Hall
  • EV Group #1225 South Hall
  • SPTS #1131 South Hall
  • SUSS MicroTec #1701 South Hall
  • NEXX Systems #1125 South Hall
  • S.E.T. #1045 South Hall