Herb Reiter

After more than 20 years in technical and business roles at semiconductor and EDA companies,…

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Figure 1: Bill Chen’s hardcopy of HIR Version on3 (Photo: Herb Reiter)

The 3rd Annual Heterogeneous Integration Roadmap (HIR) Symposium confirms it: Heterogeneous Integration is the best way for the semiconductor industry to achieve $ 1 Trillion in revenues. SEMI hosted the event at its headquarters in Milpitas. Almost 200 IC design and manufacturing experts joined, to celebrate the release of the 2019 edition of the HIR last October (Figure 1), review the Technical Working Groups’ (TWGs) progress towards the 2020 edition and discuss how to expand the TWGs’ efforts to further increase the value of this worldwide effort for our industry.

HIR Stimulates Pre-competitive Collaboration

ASE’s Bill Chen opened the symposium, welcomed all participants and outlined the importance of all HIR efforts for identifying the long-term technology requirements for advancing the electronics industry. Also, he stated that the HIR’s primary objective is to stimulate pre-competitive collaboration among industry, academia, and government to accelerate progress.

Chen introduced key representatives from the following organizations, supporting the HIR:  IEEE, IEEE’s Electronics Packaging Society (EPS), IEEE’s Photonics Society, Electron Devices Society, The American Society of Mechanical Engineers (ASME) and our host and contributor, SEMI.

Figure 2:Ajit Manocha (Photo: Herb Reiter)

In addition to this impressive list of supporting organizations, Chen had another motivator for the audience: In his welcoming address Ajit Manocha, SEMI’s president, and CEO outlined how SEMI contributes to the HIR. He described SEMI’s rapidly broadening membership – far beyond manufacturing – as well as the importance of heterogeneous integration on our path to $ 1 Trillion ($ 1,000,000,000,000) in annual semiconductor revenues in the next 10 to 15 years.

$1 Trillion in Revenue

The next speaker, Nicky Luu, Etron’s founder, chairman, and CEO, is a key supporter of HIR efforts in Asia. He emphasized that artificial intelligence (AI). machine learning (ML) and 5G will be major revenue drivers towards $ 1 T – enabled by heterogeneous integration.

Pradeep Dubey, Intel Senior Fellow, and Director Parallel Computing Lab explained that machines are no longer relegated to crunching numbers, but also make more and more of the decision, previously reserved for humans – example: autonomous vehicles. To perform their jobs well, machines need accurate models and real-time data, which is highly heterogeneous. Considering the increasing shortage of human talent, machines can and will take on more work and responsibilities, eventually, even write software to run themselves.

TWG’s Reports Available for Download

Following these keynotes, Chen and Bill Bottoms, also a key supporter of HIR, introduced representatives of most of the 23 TWGs to present their progress towards HIR Version 2, planned for release in October 2020. Here you can download, at no charge, the Version 1 TWG reports you’d like to study. If you would like to influence the direction of a specific TWG and contribute to their efforts, please complete this form.  SEMI’s Paul Trio represented Tom Salmon, who was out of town during this symposium. Bottoms, Chen and Salmon jointly head the worldwide HIR efforts. Chen encouraged the attendees to view/download relevant HIR chapters here.

Focus on Chiplets

David C. Kehlet from Intel (formerly with Altera) emphasized the importance of chiplets, briefly described Intel’s Embedded Interconnect Bridge (EMIB) solution as well as Intel’s royalty-free AIB interface technology and PHY IP. Kehlet pointed out that DARPA’s CHIPS program encourages the development and use of chiplets.

Bapi Vinnakota from Broadcom outlined the Open Compute Project’s (OCP) Open Domain-Specific Architecture (OSDA) and its value for developing domain-specific accelerator chiplets.

A major part of Friday was dedicated to brainstorming sessions between design and manufacturing experts and the exchange of ideas between these groups.

Key Takeaways

The many contributing industry organizations and the progress industry experts made in the last decade is clearly remarkable. The symposium’s invited presenters conveyed that many other industry programs are either building on the HIR efforts or complementing them. The many pointers in this text allow you to quickly and efficiently “check” what this blog describes.

On a personal note: In Spring 2008, when I chaired the first 3D-IC Working Group meeting for the Global Semiconductor Alliance (GSA), some of my closest friends pulled me aside and asked: “How is your mental capacity these days? We worry about you and suggest that you should retire.  What you are dreaming about will never happen!” In more recent years most of them apologized and asked: “How did you know 5 / 8 / 10 years ago that this technology will be a big success?” My answer always was: “Our engineering experts can solve every problem, even overcome the end of Moore’s Law as we used to know it for 50 years. All they need is management support.”

The worldwide and highly visible success of the HIR efforts, demonstrated at this symposium as well as other 2.5/3D-IC breakthroughs announced at other industry conferences in recent years confirmed that my trust in our engineering experts was correct. Regarding management support I would like to ask for support of pre-competitive efforts, like HIR, more emphasis on design and manufacturing standards as well as more open software and hardware IP. 1 Trillion US Dollars of annual semiconductor revenue is an ambitious goal, let’s work together to reach it before the 10 to 15 years Manocha projected. I am confident he wouldn’t mind!

The next HIR meeting will be held during ECTC in Orlando, May 26 to 29, 2020. There will also be an HIR workshop on July 19 in Palo Alto. During SEMICON West in San Francisco, there will be an HIR meeting on July 21 to 23. Thanks for reading…Herb