Phil Garrou

Dr. Philip Garrou is a subject matter expert for DARPA and runs his consulting company Microelectronic Consultants of NC in the RTP NC area. He is well known for Insights…

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As it has in recent years, SEMICON Europa 2019  featured a dedicated Advanced Packaging Conference. In this and my next post, we will look at some of the key presentations.

In Jan Vardaman’s TechSearch presentation “Packaging Trends for Artificial Intelligence (AI)” she noted that the following package types would be required:

  •  Automotive autonomous driving
  • NVIDIA DRIVE PX Pegasus (4 GPUs packaged in FC-BGAs on a board)
  • Tesla processor (FC-BGA?)
  • Accelerators for data centers
  • Google (ASIC + HBM2 on Si interposer)
  • NVIDIA (GPU + HBM2 on Si interposer)
  • Intel Nervana (ASIC + HBM2 on Si interposer)
  • Intel Stratix10 (FPGA + HBM2 on EMIB)
  • Xilinx UltraScale + (FPGA slices + HBM2 on Si interposer)
  • Baidu (ASIC + HBM2 on Si interposer)
  • Smartphones processors with AI features:
    • Apple application processor (InFOPoP)
    • Qualcomm Snapdragon (flip-chip in MCePPoP)

She also identified some of the components in Tesla’s Autopilot Board (Figure 1):

packaging trends for artificial intelligence

Figure 1: Tesla’s autopilot 2.5 board. (Courtesy of Jan Vardaman)

Vardaman says that the silicon interposer market is being driven by:

  • AI accelerators in datacenters to increase to 50% by 2020
  • Network systems
  • Graphics market

The largest silicon interposer available from TSMC today is 2X reticle size, or 2,500 mm2 , which has room for two, 600mm processors plus 8 HBMs in the 75mm x 75mm package.

NVIDIA’s GPU with Cu pillar mounted on a 100µm-thick silicon interposer with TSVs using TSMC’s CoWoS process is shown in Figure 2. It has 4 HBMs with 8 DRAMs per stack plus logic layer mounted on the silicon interposer (HBM with 55µm pitch). The silicon interposer is 34 mm x 43 mm with 1.1µm lines and 1.6µm space. It is packaged on a 55mmx 55mm laminate substrate with 130µm pitch C4 bumps.

Figure 2: NVIDIA’s GPU with Cu pillar mounted on a 100µm-thick silicon interposer with TSVs. (Courtesy of Jan Vardaman/NVIDIA)

Vardaman concludes that there is no one package solution for all AI applications. Choices include:

  • Silicon interposers
  • Embedded bridge (EMIB)
  • Flip-chip BGA with a laminate substrate
  • FO on Substrate
  • FC-CSP, InFO, and future PLP for mobile and consumer
  • FC-BGA for automotive AI

SEMI’s 2020 Advanced Packaging Line-up

Tom Salmon, who chaired the conference, listed SEMI’s Advanced Packaging Programs to be on the lookout for in 2020:

  • 3D & Systems Summit (Jan) –Dresden, Germany
  • SEMICON Korea (Feb) –Interconnect Package at SEMI Technology Symposium (STS)
  • SEMICON China (Mar) –Advanced Packaging Seminar & Tutorials
  • SEMICON Southeast Asia (May) –Advanced Packaging Sessions
  • SEMICON West (Jul) –Advanced Packaging Sessions
  • SEMICON Taiwan (Sep) –Advanced Packaging Forum, SiP Global Summit & Tutorials
  • Strategic Materials Conference (SMC –Sep) –Advanced Packaging Session
  • SEMICON Europa (Nov) –Advanced Packaging Conference
  • SEMICON Japan (Dec) –Advanced Packaging @ STS

Additionally, SEMI Will celebrate its 50th Anniversary this summer at SEMICON West in San Francisco.

Also in the advanced packaging space, Salmon  noted that SEMI tracks market data on the following:

    • Organic substrates
    • Leaframes
    • Mold Compounds
    • Underfills
    • Bond wire
    • Encapsulants
    • Solder balls
    • WLP dielectrics
    • Thermal interface materials

For all the latest on Advanced Packaging stay linked to IFTLE……………………………………

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