Heterogeneous Integration Makes an End Run Around 7nm Silicon at SEMI ASMC 2017

Heterogeneous Integration Makes an End Run Around 7nm Silicon at SEMI ASMC 2017

I like to think that someday soon a perfectly ripe tomato growing on a vine is going to signal its condition via the 5G network to an AI who knows I love heirloom tomatoes at their peak; my AI will place an order for me based on standing instructions (after first confirming I am indeed expected home that evening, and that I already don’t have too many heirlooms on the counter), and an autonomous vehicle (maybe it’s a drone?) will be dispatched to a certain farm field, where a certain fieldworker will hand over the plump, ripe treasure (blockchain payment transaction running in the background) to the Level 5 AV, which will whisk what is now my tomato back to my home, making it available for my evening meal. Yummm!

 

Science fiction fantasy a la “There Will Come Soft Rains,” by Ray Bradbury? Not really, I confirmed last month; every link in the chain needed for that ripe tomato to reach my home is available here today or will be by the decade’s end, a scant few years from now.

I had the honor and privilege to serve, once again, as the panel discussion moderator at SEMI ASMC 2017 which was held, once again, in lovely Saratoga Springs, NY, the week of 15 May. Along with record attendance this year and a very high quality to the papers, posters, keynote talks, tutorial, and networking opportunities at the conference, ASMC 2017 featured two panelists squaring off, so to speak, on prospects for the 7nm process node.

You couldn’t have asked for a better selection of panelists than the selection we had: Jayachandran (Jaya) Bhaskaran, Vice President, Infineon Technologies AG; Bill Miller Vice President of Engineering, Qualcomm; Subramanian (Subu) Iyer, Distinguished Chancellor’s Professor, Electrical Engineering, UCLA; Rob O’Reilly, Senior Member Technical Staff, Analog Devices; and Thomas Sonderman, VP & GM, Software Business Unit, Rudolph Technologies.

And you couldn’t have asked for a better audience either, the whole idea of these ASMC panel discussions being to engage in as much back-and-forth as possible between panelists and the audience, whom we refer to, en masse, as “The Sixth Panelist.”

The ASMC 2017 attendees took their role to heart. As did the panelists.  A good time was had by all.

Our working mandate for the panel discussion was this:

The semiconductor industry made a conscious decision to terminate further updates to the International Technology Roadmap for Semiconductors (ITRS) following the publication of the 2015 Edition. After 23 years of ITRS guidance “to ensure cost-effective advancements in the performance of the integrated circuit and the advanced products and applications that employ such devices,” we might not be seeing as far ahead as we once comfortably did.

Or maybe we need a different way of looking?

IBM, Intel, Qualcomm, and others have identified an important handful of markets likely to be the next “big things” for semiconductors – 5G, automotive, internet-of-things (IoT), industrial internet-of-things (IIOT) healthcare, and artificial intelligence (AI) are among the leading contenders.  It may be that increasingly complex system-on-chip (SoC) solutions implemented in 7nm node manufacturing serve these markets well, but it could also be that another way of thinking, namely a heterogeneous integration way of thinking, will become increasingly prominent. And if this is the case, our forward vision might well be found in the new Heterogeneous Integration Roadmap (HIR).

Join industry experts from forward-looking companies at the SEMI ASMC 2017 panel discussion as we debate which next thing is The Next Big Thing, what that means for semiconductor manufacturing technologies, how we as an industry will be challenged to respond, and how the HIR is going to help cut through the fog and make the way forward become comfortably clear again.

Think again about how my ripe heirloom tomato got from farm to table in 2019: we needed to have dedicated sensors (Rob, ADI); we needed to convert big data into actionable intelligence (Tom, Rudolph); we needed 5G communication (Bill, Qualcomm); we needed an autonomous vehicle (Jaya, Infineon); and, in many cases, we needed to integrate different semiconductor technologies into the low-cost (or “right-cost”) system-in-package solutions that collected information, acted on it, and passed on a message somewhere further down the line (Subu, Heterogeneous Integration).

Probably, a 7nm process node SoC isn’t going to be the right engine for all the smartness built into my ripe tomato example, because the 7nm SoC is just going to be too darn expensive, @ $400M+ design cost alone, but I’m willing to bet that AI / actionable intelligence will benefit from multi-billion transistor GPU architectures.

So will autonomous vehicles.

But a multi-billion transistor graphics processing unit (GPU) isn’t something you would just leave out amongst the vines to babysit tomatoes.

I said we had two panelists square off about 7nm technology; one, Bill Miller, adamant about the need, and hungry for 7nm-based silicon products, and the other one, Subu Iyer, just as certain cats can be skinned another way, using heterogeneous integration.

Could they both be right? Is it to be the lady, or is it to be the tiger?

Or is it even either/or?

I leave it with all of you.

From Santa Clara, CA, thanks for reading. ~PFW