Image Courtesy of TSMC Ltd.

TSMC’s OIP Symposium 2016

After a fairly long vacation it’s very hard to get back to work. That’s why I was really glad that this year’s OIP Symposium helped me – right after touring Europe for 3 weeks – to finding my groove again. Allow me to share some of my observations at and thoughts about the Symposium, from my “More-than-Moore EcoSystem builder” perspective.

The collaborative innovation programs TSMC started with their first reference flow almost 20 years ago, and persistently broadened as well as improved since, are clearly paying off. They complement TSMC’s many strengths as the largest wafer foundry and assure that the needed ecosystem develops in parallel with every new TSMC technology. This collaborative innovation model enables customers to fully utilize a new technology right away and allows TSMC to ramp up production quickly. Most importantly, both supplier and users enjoy fast returns of their investments (= quick ROI)!

The TSMC presentations not only focused on their portfolio of mature CMOS process capabilities, but also covered the wide range of development efforts towards smaller geometries, composite materials, advanced packaging as well as more application specific solutions. TSMC also showed which major EDA and IP vendors are contributing to the many PDK and design flow development efforts. They even won Dipesh Patel, GM and EVP for ARM’s Incubation Business, to express on stage how important the good cooperation with TSMC for the largest IP vendor is.

Here are some specifics conveyed in the TSMC presentations:

  • David Keller, EVP of TSMC North America, welcomed all in his brief opening speech; showed the area, power, and performance benefits of the 16nm production process versus 28nm; and highlighted TSMC’s ability to ramp up new process technologies very quickly — as short as one quarter to 60,000 wafers per month. Keller emphasized up front that TSMC is committed to meet the significantly different requirements of mobile, high-performance computing (HPC), automotive and Internet of Things (IoT) opportunities.
  • Jack Sun, TSMC’s CTO, talked about the FinFET developments for logic and memory, announced 10nm high-high volume manufacturing (HVM) to start in Q4, 2016, and promised that TSMC will be ready for 7nm risk production in Q1, 2017. Sun confirmed that TSMC’s 55, 40, 28 and 16nm ultra-low power processes – ideal for IoT – are in production now. He outlined TSMC’s development efforts for RRAM, MRAM, BCD, GaN on Si and for CMOS image sensor (CIS), as well as the ongoing work to meet the stringent advanced driver assist system (ADAS) requirements for automotive customers. Last, but not least, Sun positioned the high-performance chip-on-wafer-on-substrate (CoWoS) package versus the low cost integrated fan-out (InFO) solution and explained their important roles for system scaling.
  • Cliff Hou, Vice President, Research & Development / Design and Technology Platform, detailed with many slides which major EDA vendors are qualified for specific design steps and process technologies, and talked about design enablement efforts for 7nm technology. He mentioned that TSMC is also working on platforms and application-specific design flows. I interpret this as a move to bring key customers into TSMC’s Open Innovation Platform.

The CoWoS packaging capability is a perfect example of TSMC’s commitment to more complete solutions and the cooperation with high-performance customers. Likewise, TSMC’s low cost InFO-PoP technology has been developed for the iPhone 7, and is now in very high-volume production for this customer. Both of these programs demonstrate the increasing value of IC packaging technology and show the importance of working with customers on application-specific unique solutions as well as on customizable platforms.

TSMC made the second half of the morning and all afternoon available to partners for presenting their capabilities in support of TSMC’s broad technology offering. In three tracks (EDA // IP // EDA, IP, Services) these partners outlined, in front of many mutual customers, their successful cooperation with TSMC as well as how partners’ products and services complement TSMC’s capabilities. Most of these presentations are included in the color handout every attendee received at the registration desk.

Like in previous years, a number of partners (actually fewer than before) showed their capabilities on the exhibition floor and engaged with current and potential customers to answer questions and discuss opportunities.

You must have noticed that I invest a lot of time and money in attending (also contributing) to industry conferences. Here is a list of upcoming conferences I plan to attend and my reasons why I recommend them to you:

iMAPS International in Pasadena, CA, from Oct 10 – 13   

  • Monday: A large number of new, 2-hour Short Courses about advanced packaging, materials and reliability
  • Tue- Th: In-depth presentation about applications, assembly steps, modeling, design & manufacturing flows

IWLPC  in San Jose, CA, from Oct 18 – 20

  • FOCUS: Wafer-level packaging, the by far fastest growing packaging technology
  • Expert panel discussions, Fraunhofer & GeorgiaTech keynotes, detailed technical messages

3D CAD Conference in San Francisco, CA, Nov 9 – 11

  • System integration benefits of 2.5/3D-IC Technology, a range of application examples
  • Experts present new technologies and materials and suggest how to solve common challenges

MEPTEC Conference in San Jose, CA, on Nov 14  

  • ITRS Roadmap has been replaced by the Heterogeneous Integration Roadmap; why and how will be addressed
  • Keynote presentations by IC packaging experts; panel discussion about this major, pre-competitive HIR program

3D ASIP in Burlingame, CA, from Dec 13 – 15        

  • Oldest and largest 2.5/3D-IC focused, highly technical conference; covering manufacturing AND design
  • Advanced technologies, equipment and material capabilities for commercial and military applications

Here is one more way to get you either started or up-to-date on the latest 2.5/3D-IC design and manufacturing capabilities: The Multi-die IC User Guide I compiled in Spring 2016, with in-depth inputs from more than 35 companies. It’s posted at the Electronic System Design Alliance’s website since last June. To download your own free soft copy simply click here.

Over 300 persons, from major companies all over the world, have downloaded this most comprehensive 2.5/3D document already. Check it out and give me your feedback, to make the Spring 2017 edition even more useful for you !  ~ Herb