I can’t believe it’s already been a year since I last posted my annual guide to 3D at SEMICON West.  One thing I’ve noticed in scanning the “regulars” (SEMI and SEMI partner events) is that all the agendas are  much less focused on 3D integration developments. I think there are a couple reasons for this. First of all, many suppliers are in a holding pattern waiting for high volume manufacturing of 3D devices before they invest more into it. Secondly, after years of pouring in the development funds, technologies are now mature. There’s nothing more to do until the orders start rolling in.  On the manufacturing side, it’s that wait-and-see phase. Some say that this is a good sign. It means 3D is ready for mainstream and there’s less talk about it as a recent innovation. That being said, there’s still plenty being discussed at SEMICON West that applies to 3D integration; some directly, and some indirectly. Here’s what I plan on checking out during the week:

Monday, July 7, 2014
I always think of Monday of SEMICON West week as the “pre-game” show. For the past few years I’ve chosen to attend imec’s International Technology Forum over the SEMI/Gartner Market Symposium, as the two events run concurrently. This year, I’m changing it up a bit, and attending the latter, specifically because of two presentations: Sam Wang, VP Research, Gartner will discuss How Foundries will Compete in a 3D World. The 3D world being discussed included both 3D transistor structures and 3D packaging processes. Wang will be followed by Jim Walker, who’s talk titled Foundry vs. SATS: The Battle for 3D and Wafer Level Supremacy, promises to provide some interesting insight on which is better suited to provide wafer-level and 3D processes. I already can’t wait to write about it. The keynote, which will be delivered by Sunit Rikhi, VP Technology and Manufacturing Group, General Manager, Intel Custom Foundry Intel, will explain Intel’s foray into custom manufacturing, essentially competing with pure-play foundries for fabless contracts.

Imec’s ITF theme this year is Novel Dynamics in Consolidated Semiconductor Landscape. The robust program takes a high-level perspective of the R&D challenges, the ecosystem, and the semiconductor roadmap; and hones in on metrology, and materials driving interconnect scaling. While I’m sure there will be mention of 3D, it will likely be as a sub-set of the big picture.  This is an invitation-only event.

Tuesday, July 8, 2014
Most of what’s being presented during SEMICON West that applies to 3D integration takes place on Tuesday, both on-site and off site. Mark Adams, president of Micron, will open the show with his keynote, Innovation and Partnership: Driving the Future of the Semiconductor Industry.  In the 3D IC world, Micron = hybrid memory cube (HMC) = HVM 3D IC opportunity. Yeah. I want to hear what he has to say!

From there I will head off-site to the St. Regis, where SUSS MicroTec is hosting its annual technology forum focused this year on 3D integration and wafer level packaging. The event runs from 9:00-4:30, and features presentations on 3D market trends and WLP market trends by Rozalia Beica, Yole Développement; and Jan Vardaman, TechSearch International Inc.; respectively. Steve Bazuk, of Qualcomm, will deliver a keynote on Challenges and Directions in Mobile Device Packaging; and technology updates will cover temporary bond/debond processes and materials, process control, lithography, laser drilling and more.

What not to look for this year is SEMATECH’s 3D Metrology Workshop. Instead SEMATECH has partnered with SEMI on the metrology segment of the new Semiconductor Technology Symposium (STS), which focuses on the big trends shaping near-term semiconductor technology and market developments in areas including 450mm, advanced processes and materials, lithography, metrology, yield, design packaging, and test. STS consists of parallel  morning sessions running from 9:00am-12:00pm; one on Innovations and Drivers in Metrology, and the other on Mobility and More –The M&Ms of Cost Beneficial Advanced Packaging.  The panel in the latter session addresses fan-out wafer level packaging technology (FOWLP) and its role in miniaturization, and features panelists from Amkor, Nanium, Deca Technologies, STATS ChipPAC and TSMC.

After a networking lunch, STS breaks off again into parallel sessions from 1:30-4:30. The Yield Session focuses on CMOS scaling issues to 20nm. Embracing what’s NEXT – Devices & Systems for Big Data, Cloud and IoT is more my speed, focused on packaging solutions to meet next-generation cost and performance requirements. I would bet that there’s some discussion of 3D in the presentations by Dr. Tao Zhang, Cisco Systems; Raj Master, Microsoft; and Bill Bottoms of the ITRS; as well as the panel featuring Ron Huemoeller, Amkor; Calvin Cheung, ASE; and Doug Yu; TSMC. (Looks like I’ll be dividing my day between SUSS’s event and this one.)

Also on Tuesday from 1:30-3pm is a TechXpot session on 3D NAND – another area of 3D we’ve been covering on 3D InCites. (Rather than clone myself, I will count on guest bloggers who have more knowledge about 3D NAND than I do to attend and write about this one.)

Tuesday 3D options wrap up with Leti Day, an off-site, invitation-only event that takes place from 5-8pm at the W Hotel. The agenda features a presentation on the research center’s work in monolithic 3D (M3D), by Oliver Faynot, Leti’s device department director.

Wednesday, July 9, 2014
Wednesday morning from 9-noon, one of the parallel STS sessions focuses on Design for Test (DfT), presented by the EDA consortium. Presentations will address how complexities in product design and manufacturing, as well as higher levels of product integration (SoC, SiP, multi-core, 3rd party IP/cores, 3D IC, FinFet devices, etc.) requires new DfT data volume and test execution time, as well as reduction strategies and innovations for these next generation, most challenging pin-limited designs.

Thursday, July 10, 2014
Speaking of 3D test, TestVision 2020, co-located with SEMICON West, runs from Wednesday, July 9, to Thursday, July 10, and features the session, 2.5D / 3D Probe & Test: Test Program Game Changers? on Thursday morning, July 10, from 9:45-10:45.

And let’s not forget the most important 3D event of all, the 2014 3D InCites Awards Breakfast, sponsored by Micron, takes place from 8-10am on Thursday at the Impress Lounge above Moscone North. Reserve your spot and come congratulate your colleagues on their achievements and enjoy some targeted networking with the movers and shakers in the 3D integration space.  Keynote speaker, Bryan Black, Senior Fellow at AMD, will discuss the cost/performance benefits of 3D SOCs. This year, we’ll be awarding a Reader’s Choice Award, based on an online poll. Don’t forget to vote; only two more weeks to go! Hope to see you there! ~ F.v.T.

Francoise von Trapp

They call me the “Queen of 3D” because I have been following the course of…

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