READY – AIM – FIRE! Predictions for 2.5D ICs in 2014

READY – AIM – FIRE! Predictions for 2.5D ICs in 2014

Major SoC vendors, like Intel and IBM, started development work on 3D ICs more than a decade ago, but so far, economics have discouraged them from starting volume production.

Ho-Ming Tong, CTO, ASE, and his team realized a few years ago that vertical stacking of logic die and/or heterogeneous functions did (and still do) require major engineering efforts and significant business model changes before our ecosystem will allow broad deployment and cost-effective volume production of 3D ICs beyond stacked memories. Only memory vendors have so far provided 3D IC samples, demonstrated benefits of through silicon via (TSV) interconnected memory stacks and are in the process of ramping volume production.

Tong suggested combining logic die and/or heterogeneous functions side-by-side on an interposer instead of stacking die on top of each other, and coined the term “2.5D IC” for this technology. What appeared at first sight to be a compromise or, best case, only a small step towards the “real thing;” vertically stacked die in 3D-ICs, turned out to be a very viable alternative and for many applications a more practical and less engineering-intensive solution, compared to vertically stacked die. Interposer-based, so called “2.5D ICs” are now mainstream, accepted widely and far outnumber 3D-IC design starts to date.

READY to utilize 2.5D – at the beginning of 2014: The latest conferences I attended (RTI’s 3D ASIP conference in Burlingame, CA, and Georgia Tech’s 3rd Annual Interposer Workshop in Atlanta, GA) confirmed my expectations that our ecosystem is really ready for developing and deploying 2.5D solutions. Here are a few compelling data points:

  • Materials and equipment vendors as well as Fabs and OSATs are ready to support interposer volume production.
  • Unlike 3D ICs, interposers only need TSVs to connect active die with package substrates. Existing die don’t have to be redesigned to be mounted on an interposer. Only if further die area, power reductions, performance enhancements, or other changes are needed, a redesign is recommended to reap the full benefits of 2.5D technology.
  • Dozens of 2.5D prototyping- and evaluation/qualification efforts are currently ongoing at IC vendors and system houses to get familiar with this new technology, evaluate strengths/weaknesses and plan deployment.
  • The dreaded “Memory Wall” is finally being torn down by combining (mostly multi-core) CPUs and memory stacks on interposers. The big memory vendors (Samsung, Micron and SK Hynix) as well as Tezzaron, a specialty memory vendor in Naperville, IL, are sampling vertically stacked memory die widely and are firmly committed to ramp volume production of 3D memories in 2014. In addition, IP vendors, like Invensas and Rambus, offer 2.5D reference designs for tearing down the memory wall constraining design(s).
  • IC designers and equipment vendors have learned how to combine currently available EDA tools with some in-house developed tools to implement, verify, and probe passive interposers as well as test the interaction between die mounted on silicon or organic interposers.
  • Xilinx’ success with their rapidly growing Virtex 7 product family (combining FPGA slices and/or SERDES die on an interposer) demonstrates the value of homogeneous- and heterogeneous die-level IP integration.

Yes, 2.5D is just like other new technologies I have worked on: customers would like, in addition to all the technical benefits 2.5D technology offers, cost reductions versus SoCs right away. However, they appear to be realistic and plan to use 2.5D technology initially for less cost-sensitive applications. Bottom line: 2.5D technology is ready and actually being designed in now, e.g. for graphics, networking, and computing applications to increase performance, reduce power dissipation, form-factor, etc.

AIM and cost-reduce – during 2014: Based on my observations outlined above, I expect 2014 to be the year 2.5D solutions are aimed at many more applications that need higher bandwidth, shorter latency, lower power dissipation, smaller form-factor, easier heterogeneous integration and/or other benefits 2.5D-ICs offer over PoPs, SiPs or PCB-mounted SoCs. Many companies will enjoy a steep 2.5/3D learning curve and start developing 2.5D ICs in 2014.

Why do I expect this trend? Because I finally see that packaging experts, who have been the primary drivers of 2.5D projects within their companies, are getting more attention and respect for their 2.5D expertise. SoC and even system designers are now working with their packaging teams to plan and implement new system solutions utilizing 2.5D technology. This company-wide cooperation will also quickly lead to integration of passive devices (e.g. capacitors and inductors) in interposers and may suggest moving even active components “down” to interposers.

The resulting area- and cost reductions of logic die, manufactured in very advanced technology nodes, will make passive interposers and especially ones with active circuitry very cost competitive.

The many ongoing 2.5D designs in 2014 will also allow EDA vendors to see clearly what additional implementation and verification tools are needed and will sell in sufficient volumes to guarantee positive ROI.

New in-house developed tools, possibly merchant tools, will enable system-designers and project leaders to efficiently and accurately plan and partition entire systems. They’ll help to analyze different options, such as:

  • Continue Moore’s Law: Implement logic and other functions in an even smaller feature size process or
  • Add 3D memory next to an SoC on an interposer versus a “far away” memory IC on a PCB and/or
  • Add dedicated Analog/RF functions, MEMS, sensors,… in die-form on an interposer, use PoP or SiP or dedicated ICs on a PCB and/or
  • Reduce the SoC die area and cost by moving blocking capacitors, inductors, ESD structures, entire I/Os (including SERDES), power management circuits, MEMS, sensors and other functions to an interposer or rely on several dedicated ICs and passives, assembled on a PCB

The highly desired and always needed cost-reduction efforts will not only focus on interposers and die mounted on them, but also reach into packages, e.g.:

  • Can a package substrate assume the role of an interposer or an interposer replace a package substrate?
  • Can currently highly complex (and costly) PCBs be simplified by moving interconnections into package substrates and/or interposers?
  • Can connectors and cables between PCBs get reduced by packing more functionality into highly integrated, lower power 2.5D and/or 3D components?
  • Can simpler, smaller, even fewer PCBs be used?
  • Can power dissipation be reduced significantly with 2.5/3D ICs, to save cooling cost?
  • Can a smaller power supply and/or cheaper battery or smaller chassis be used for the new system?

FIRE and win – end of 2014: After developing production-worthy 2.5D designs during 2014, IC vendors and system houses will demonstrate – no later than year-end – new product features as well as performance and power benefits to customers. Finally, they can fire the signal to start volume production and generate significant revenues.

Just like with other new technologies, early market entrants will win not only higher margins and larger market shares, but also the opportunity to start working with innovative customers on the next, even more advanced product design earlier than competitors.

Your feedback, please: When you are READY, please AIM, then FIRE. ~ H.R.