Design and Modeling for 3D ICS

For almost 50 years the semiconductor industry has practiced continued shrinking of transistor feature sizes and has been able to pack, with every new process generation, more functionality, at lower cost, onto a single piece of silicon in one IC package. However, physical limits to shrinking and rapidly increasing cost of this methodology have triggered the development of alternatives that combine multiple pieces of silicon (‘dice’, each one a ‘die’) in one package. These approaches have proven technically viable and cost-effective. Especially interposers and 3D ICs, the subjects of this book, are very attractive solutions to continue on the rapid semiconductor innovation path.
Combining multiple dice in one package shifts a big portion of the value creation from silicon design to package development and demands new design- and manufacturing methods.

Georgia Institute of Technology in Atlanta with two centers on electronic packaging has focused on IC packaging research since 1994 which has led many packaging-related innovations, including interposer design and 3D ICs. The book’s author, Professor Swaminathan teaches at Georgia Tech and is CTO of E-System Design. His former student Ki Jin Han, Ph.D, is now Assistant Professor at the School of ECE at UNIST in Korea. They share their IC package development expertise with the readers of this book.

Chapter 1 outlines the reasons why following Moore’s Law (continued transistor shrinking) will no longer meet technical and/or business requirements for many applications. The chapter highlights the many benefits combining multiple dice in one package and interconnecting them with through silicon vias (TSVs) offer, e.g.: Higher bandwidth, shorter latency, lower power dissipation, lower package height, easier integration of heterogeneous functions – compared to utilizing traditional solutions. It also explains why the close proximity of homogeneous and/or heterogeneous dice in one package makes previously minor design- or manufacturing challenges more difficult to solve. Chapter 1 also describes the characteristics of different materials and explains why electrical-, thermal-, mechanical- and other effects (ETM) need to be analyzed throughout the planning, implementation and verification phases. Early detection and resolution of ETM issues allow multiple options to be considered quickly, while later detection limits the search for viable options. Last, but not least, it compares benefits and drawbacks of different approaches to create reliable and cost-effective solutions.

This chapter is useful for engineers and engineering management to familiarize themselves with the rapidly emerging interposer- and 3D IC technology. It also briefly describes a 3D IC “Path Finding Tool” that can accelerate interposer- and 3D IC modeling- and design efforts.

Chapter 2 describes a number of numerical methods for parasitic extraction and simulation of cylindrical shapes (TSVs and TGVs), spherical shapes (solder balls) and bonding wires interconnecting dice and package substrate. Although this chapter covers modeling and simulation concepts useful for EDA tool developers; for the silicon/package designers it highlights why new concepts are required to accurately and quickly analyze package solutions in which hundreds to thousands of vias, balls and bond wires will be used.

Figure 1 Design and Modeling for 3D ICs
Figure 1: Through Glass Via (TGV) spacing in glass: a) at 70 um spacing, b) at 250 um spacing


Figure 2: Near end and far end cross talk comparison.
Figure 2: Near end and far end cross talk comparison.

In chapter 3 the authors dive into practical considerations for modeling of TSVs and show designers how several types of TSVs exhibit different electrical and electromagnetic behavior, based upon substrate electrical parameters (including biasing) as well as physical topologies (via tapering and pitch).

Chapter 4 discusses signal integrity challenges, coupling between TSVs, responses of power and ground planes and comparisons between silicon- and glass interposers. The chapter initially discusses how substrate processing (process tuning) improves or degrades TSV performance, ends with a discussion on cross talk variance and suggests various measures designers can use to maximize electrical performance.

Figure 3 Insertion loss variation with process parameters In a) L varies: R = 10 um, D = 50 um, dox = 100 nm, L = 50 um, 100 um, 150 um In b) dox varies: R = 10 um, D = 50 um, L = 100 um, dox = 50 nm, 100 nm, 150 nm In c) D varies: R = 50 um, L = 100 um, dox = 100 nm, D = 50 um, 75 um, 100 um In d) R varies: L = 100 um, D = 50 um, dox = 100 nm, R = 5 um, 10 um, 15 um GG P3 P1 Formatted: Font: 12 pt, BoldFormatted: Font: Bold
Figure 3: Insertion loss variation with process parameters In a) L varies: R = 10µm , D = 50µm, dox = 100nm, L = 50µm, 100µm, 150µm In b) dox varies: R = 10µm, D = 50µm, L = 100µm, dox = 50nm, 100nm, 150nm In c) D varies: R = 50µm, L = 100µm , dox = 100 nm, D = 50µm, 75µm, 100µm In d) R varies: L = 100 um, D = 50µm , dox = 100 nm, R = 5µm, 10µm, 15µm
Figure 4a: Insertion loss across the 20 x 20 TSV array showing 0.6 dB spread. Size of array analyzed does matter besides location!
Figure 4b: NEXT (cross talk) across the 20 x 20 TSV array showing 50 dB spread. Signal / PDN assignments to specific TSVs matter!
Figure 4b: NEXT (cross talk) across the 20 x 20 TSV array showing 50 dB spread. Signal / PDN assignments to specific TSVs matter!

Chapter 5 addresses power distribution and thermal management challenges and their impact on electrical performance. This chapter illustrates the reasons why power distribution and thermal management are the two primary challenges for 3DIC designers.

Chapter 6 introduces future concepts that are being investigated for power distribution that can be used to minimize supply noise and return path discontinuity effects. These methods are also useful to enable high speed communication between ICs in a package or on a printed circuit board.

This book combines in one volume most of the additional know-how IC designers need to acquire before they can take advantage of the capabilities interposers and 3D ICs offer. Understanding how multiple dice in close proximity interact with each other and with the package is essential for designing reliable and cost-effective 3D ICs and/or interposer solutions – in close cooperation with the in-house packaging experts or a supplier. The many formulas and methodology descriptions in this book make it also a very good reference book for experienced designers of 3DICs and interposer-based solutions. ~ H.R.

Design and Modeling for 3D ICs and Interposers
ISBN 9789814508599
Authors: Madhavan Swaminathan and Ki Jin Han
Publisher: World Scientific Publishing Co Pte Ltd
Availability: Now, e.g. at

Herb Reiter

After more than 20 years in technical and business roles at semiconductor and EDA companies,…

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