At this year’s IMAPS International Device Packaging Conference, despite a robust line-up of speakers and presentations focused on 2.5D and 3D integration technologies, I came away feeling slightly empty handed. Concerned that this was just my own perspective after years of 3D IC total immersion, I asked around to take the pulse of the other attendees, many of whom are 3D IC ‘regulars’ like me. Echoing my own sentiments, they went on to theorize the possible root causes. But ultimately it comes down to the reality that we have reached that point in technology maturation that despite a few remaining pain points, it’s its all over but the waiting for that first big PO.
This observation is in no way meant to be disparaging of IMAPS DPC program. In fact Rajiv Roy, of Rudolph Technologies, commented during the 3D Panel discussion, that this year all the action was across the hall in the flip chip and wafer level packaging sessions, where competing technologies such as embedded die were reporting all kinds of advancements with smaller pitches and thinner profiles.
That said, the week was not without its refreshing a-ha moments as a number of presenters talked about advancements in curing the pain points as indicated by Invensas’ Sitaram Arkalgud in his keynote address. Among these are materials for temporary bond/debond; underfill material development to address thin die, finer pitches and unbalanced structures; modeling and simulation tools for thermal mechanical stress, and novel, performance-enhancing, cost-saving wet processes for TSV metallization (more on these later).
Arkalgud’s 3D IC Scorecard
Typically with technology transitions, the acceptance of a next-generation technology is catalyzed by the convergence of several factors, explained Arkalgud. Essentially, the stars align only when:
- The cost/benefit ratio of the incumbent technology becomes minimal,
- The new technology moves beyond the feasibility stage
- A robust ecosystem is ready
- Industry leaders come to consensus on a timetable
- There’s a willingness to invest.
Based on this “scorecard” Arkalgud noted that we are “well beyond feasibility”, but there’s work to be done on the cost/benefit ratio, question marks on the ecosystem, timetable consensus, and a willingness to invest.
He offered both cup-half-empty and cup-half-full perspectives. On the half empty side are naysayers pointing to cost, reliability, scalablity and supply chain readiness. In this case, scalability is not referring to gate length, but to chip-to-chip interconnects, wafer/die thickness and TSV dimensions. This type of scaling will be a key contributor to cost reduction. On the cup-half-full side, early adopters of 2.5D and 3D are in play, with prototypes ready, so HVM isn’t far behind, says Arkalgud.
When asked by Jan Vardaman, TechSearch International, what he would prioritize the list of what needs to happen, Arkulgud said the big issues are still thin wafer handling and thermal management of 3D ICs. After that, “scaling TSVs is easy.” he said.
Where’s the 3D Sweet Spot?
“What’s the first among remaining challenges to focus on?” was also the question posed by panel moderator Keith Cooper, SETNA, to kick of the 3D panel discussion, which featured Arkalgud; Vardaman; Rich Rice of ASE, Qualcomm’s Matt Nowak; and Arifur Rahman, of Altera.
Rice went straight to the heart of the matter, talking about how ASE has made the investment in capacity to manufacture these devices. “I would like to understand the sweet spot between performance enhancement and increased cost,” he commented, directing an inquiry to product architects, “How can we sell these things?” While high-end applications such as networking asics, FPGAs, and high performance graphics are moving to 2.5D, it still “looks cost additive compared with the existing solution.”
As an end-user, Matt Nowak brought up the topic of pricing versus what it “should cost”. Citing Chet Palesko’s presentation of cost modeling from earlier in the day, he said it was a good example of conservative yield assumptions, and that there’s a 20% increase in the cost of a 3D IC product thanks to yield uncertainties and profit margins. “The first products will bear a significant burden to recoup the investment,” he noted, adding that the availability of low price, TSV Wide I/O memory cubes and low price interposers will continue a process of cost reduction.
Vardaman reported back from her visit to Japan, where she says the ASET program has just concluded a project review, and has determined that remaining issues include pathfinding tools, stacking improvements, test, and the supply chain. She also pointed to Memory as the key product. “If you can make it work in Memory, you’ll gain so much understanding.” she said.
While discussion was livelier than I’ve seen other panels, likely thanks to the restorative refreshments served, there was lots of reaffirmation of a status-quo situation. Namely, that high-end applications will be the first to adopt, and as volumes grow and price comes down, POs will start coming in from manufacturers of consumer products.
As with the mainstream adoption of flip chip processes, the transition will take place when the old solutions don’t work anymore. The difference this time is that that this reality is coming on two fronts. From a packaging perspective, when there is no other way to achieve the required high-density interconnects, end-users will have to bite the bullet and invest in 3D ICs. On the front-end, when scaling hits the 14nm and 10nm nodes, it’s cheaper to disintegrate the technologies and use 3D ICs to achieve the necessary performance, explained Arkalgud. By that time, only 4 or five companies will be able to afford to manufacture at those nodes, and the rest of the world will look to 3D ICs to stay in the game.
All in all, consensus is that 3D ICs have a bright future. The remaining question is just when that future will arrive. ~ F.v.T.