Fridays just kind of creep up on you, don’t they?  It’s been a busy week in the 3D blogosphere – and not just on 3D Incites. I’m a little disappointed that nobody wanted to play the “how do you use your mobile device”  game I started on Monday with these two questions at the end of my post. So lets try again. Please post answers at the bottom in the content area here. Maybe its more of a Friday kind of game anyway.

  • Do you think tablets can or will replace laptops/PCs? 
  • What are the main tasks you use your smartphone and/or tablet for?

Here are some other interesting views on similar topics such as reviews of Microsoft’s Surface tablet, comparisons of the iPhone 5 and Samsung Galaxy 3s, etc that you might find not only informative but entertaining as well. (While not exactly about 3D IC technology, these are the volume applications 3D ICs are destined for, so it’s important to keep an eye on that market too.)

Getting down to more serious business, I came across this blog post Jerry Twomey on Electronic Design, Marketing And Technology Collide In Competitive Chip Design , in which he talks about the importance of communication between the marketing department and the chip designers, so that the marketing team doesn’t sell something that can’t be designed and manufactured cost-effectively, and likewise designers don’t design something that will never make it out of the lab into volume production. He writes “As a general rule, your design needs to be “just good enough” to get the job done. For lack of a better way of describing it, circuit designs need to hit the requirements of the system and not much more. The cheapest functional solution generally owns the market, and “over design” tends to push up power consumption or circuit area.” (I wonder, will this type of directive hold back designers from designing 3D ICS?)

Here’s another bit of advice I would heed if I were a chip designer considering 3D ICs: “Emerging market designs need a timeline strategy for front-of-the-line execution. If it’s an emerging standard, you need to be involved in developing it. In many cases, you can develop your chipset as the standard details are still being defined. If you wait until the standard is finalized to develop your design, then you’re already too late.”

If, like me, you missed the TSMC Open Innovation Platform (OIP) Ecosystem Forum Oct. 16, you’ll want to check out Richard Goering’s (Cadence) coverage of it here. I mentioned a few tidbits by way of press releases, but he gives a great overview of everything from 20nm to 3D ICs, and 14nm FinFets.

SemiMD’s Ed Sperling scored an exclusive interview with Intel’s Mark Bohr, who’s become well known over the past few months for his comment that “the fabless model is collapsing”. In Deep Inside Intel, Ed asks some probing questions about Intel’s roadmaps, advanced node issues, and its work in 3D ICs. I cherry picked two questions on 3D ICs  to comment on here, for the rest you should really read the whole interview.

  • SMD: Where do stacked die fit into your roadmap?
    Bohr: 3D stacked die have advantages, but only for certain market segments. You have to be very clear about what problem and what market segment you’re trying to serve. For a small handheld application where a small footprint and form factor is key and power levels are low, it probably makes good sense to use 3D stacking. For desktop, laptop and server applications where form factor isn’t as valuable and power levels are higher, 3D stacking has some problems that make it not an ideal solution.

While Bohr is probably correct about desktops and laptops (Intel’s market, after all) I’m not sure IBM would agree with Bohr on server applications for 3D stacking – as industry-wide its been determined that one of the 3D IC volume application drivers for wide I/O DRAM on logic is the server market.

Towards the end of the interview, Sperling circles back to TSVs in response to Bohr’s responses about interconnect becoming problematic, and the solutions being considered at Intel. He asks Bohr if he mean’s TSVs, to which Bohr responds: “Yes, and we’ve been public about exploring TSV and 3D technology for a couple years. Although there are some challenging technology aspects, the real issue is cost. Doing TSVs and stacking chips—especially these custom Wide I/O chips—is expensive. So this might be a better engineering solution in terms of density, performance and power, but will the market bear the added cost? Not all markets will bear the higher cost.”

So unless this is smoke and mirrors and Intel has something up its sleeve, its probably safe to say that Intel won’t be the first to adopt or commercialize TSV and 3D technology, or at least that’s what Mark Bohr leads us to believe.

That’s it for now. Signing off until next week – F.v.T.

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