For those of us who attended Doug Yu’s keynote address at the 3D Architectures for Semiconductor Integration and Packaging Conference in December, yesterday’s keynote at IMAPS DPC was, in the words of the immortal Yogi Berra, “déjà vu all over again”; driving home the message that yes, TSMC intends to provide full 2.5F and 3D service including chip design and fabrication, stacking and packaging. While he didn’t actually state TSMC’s intentions formally in his address titled “System Scaling Superhighway”, Yu, who is senior director of integrated interconnect and packaging, R&D at TSMC, outlined the key technologies that offer the best path to commercializing 3D integration technologies, with the implication that TSMC is well positioned to provide them all.
He extolled the virtues of copper, urging the industry to embrace copper, all the way from the transistor, IC component, and flip chip to subsystem. TSMC is well versed in the use of copper (Cu low-K dielectrics) in front end processes, and has a handle on such issues as etch, fill, O.D. and pop up issues. Yu also made a point to demonstrate the foundry’s capabilities in the back end.
“TSV is much more complex and challenging than ever before,” noted Yu. “There’s a new ballgame and a small window.” He said a conventional collaboration infrastructure is becoming harder. Integration must be simplified to reduce handling (who owns the mishandling?) and an investment beyond conventional back-end (in other words, middle-end-of-line tools and processes) is required. In short, Yu said a full spectrum of expertise is needed that includes manufacturing excellence, capacity and customer relationships where there is no competition with the customer (a thinly veiled reference to the Samsung/Apple relationship?) Lastly, he said it requires chip/package/subsystem co-design, and TSMC has this infrastructure in place. “The industry suppliers who can best leverage Cu interconnect technology expertise to provide simplified integration to manage the interfaces will win. They are the virtual superhighways,” concluded Yu.
It’s a strategy that appears to be almost impenetrable, until you consider the missing piece: Memory. Jan Vardaman posed the question that had to be asked: “TSMC does not make memory. When you talk about all the handling problems, who will handle the issues when you bring in memory from suppliers?” Yu’s response was that they are working with memory partners and partner customers on this matter.
When you put all this together with the unconfirmed rumor that TSMC will be supplying Apple’s next generation A6 processor rather than Samsung, and that processor will include 3D ICs, TSMCs strategy becomes a whole lot clearer. The question is, will other fabless customers jump on board, or will they prefer the flexibility offered by the collaboration model being promoted by the rest of the pure play foundries and OSATS? That, as they say, remains to be seen. – F.v.T.
Note that the iPad 3 came out NOT with a A6 but with a “A5x” ( still only dual ARM cores though quad GPUs ) from Samsung ( Austin ). Not sure yet though if it is built at 28 nm.
Given all the reports of TSMC on the other hand having issues at 28 nm wonder how they are faring with nVidia’s Tegra 3 that have quad ( more like 4.5 ) core processors ( larger die – lower yield ) ?
Perhaps right now they are looking at 3D stacking with TSVs primarily as a hedge against low Fab yields at the bleeding edge nodes ( 28 nm ), for much the same reason why IBM has been building 2D MCMs w/ C4 for 3 decades and now does 3D w/ TSVs.
The original report in EE Times last Fall on TSMCs 28 nm was that they wanted to :
” .. re-tape the A6 design so as to partition the SoC into separate blocks / dies .. ”
( presumably to move the IP blocks around and locate the vias so as to facilitate stacking of individual KGD made at latest but low yield node or coarser but stable node ). This seems to have gotten somewhat misinterpreted since then and so perhaps the right questions were not posed at the IMAPS sessions.
So per above scenario, tight integration w/ Memory using TSVs may not yet be a factor for TSMC ( as they would be interested in using TSVs mostly to get business for SoCs like A6 even when using low yielding bleeding edge nodes or coarser but stable Fab nodes ). TSMC would then follow a business model similar to IBM MCMs ( instead of shipping individual wafers with variable yields to the OSATs for assembly, they would themselves pick and choose the good dies from wafers, 3D stack them and then assemble them to look like a “single” chip package, thus avoid having to disclose to the outside world sensitive yield data for bleeding edge nodes.
As to integrating this pseudo “single” – chip SoC to DRAM / NAND, good ole wire – bonded PoP / PiP should suffice for couple of years even at the higher bandwidths enabled by 4G LTE.
It is the power dissipation ( battery life ) of CMOS transistors at coarser nodes stacked by TSVs that would still not be as good as that expected at 28 nm
Hi Dev –
Thanks very much for sharing your insight with the 3D InCites community. I imagine these questions would be touching on some very sensitive information that TSMC would be reluctant to discuss in a panel discussion forum, even had the questions been posed during the panel.
Francoise