3D Panel Discusses the Evolving 2.5D/3D Infrastructure

Here’s something new from previous Device Packaging Conferences – rather than a panel largely populated by members of the EMC^3D Consortium (ie: suppliers) moderated by either Jan Vardaman or Phil Garrou, the panel was populated by foundry and OSAT representatives, a fabless company, a market analyst, and  still moderated by Phil Garrou. Specifically, the panelists included Doug Yu TSMC; Jon Greenwood, Global Foundries; Remy Yu, UMC; Nick Kim, Hynix, Ron Huemoeller, Amkor; Rich Rice, ASE; Matt Nowak, Qualcomm; and Jan Vardaman, TechSearch International. This alone was a clear indicator that indeed, 3D has moved beyond what has become known as ‘powerpoint engineering’ and is headed full tilt toward commercialization.

Another sign of progress is that the industry appears to be in agreement that technology is stabilizing to focus primarily on Cu TSV middle, coming from the IDMs and foundries, with some via backside last; and that 3D stacking is focusing on 50µm Si and 5×50 µm TSV; but that interposer dimensions are likely to be varied based on intended application. (As a caveat of sorts, Nowak pointed out an alternative approach proposed by IBM that involves holding off on via formation until much of the backside processing is done, then do the via. It’s not exactly via last, but he says it creates a technology that is technology node agnostic, which has benefits.)

A year ago, the supply chain infrastructure was still shaking out. Now there are two clear models emerging. One is the full service foundry model being adopted by TSMC; the other is the collaborative model being adopted by everyone else. Greenwood said that GlobalFoundries, who entered the 3D arena a mere 18 months ago, will rely on collaborative relationships with major OSATS and key material suppliers to provide a flexible supply chain for its customers. Remy Yu said UMC is also driving an open ecosystem, and its joint development project with Elpida and Powertech is well-known.  Mention of Elpida brought up the question about the future of this project, considering Elpida’s recent bankruptcy filing. Yu responded that the engagement with Elpida and PTI is only one of several projects UMC is involved with.*

Noting that 3 seats were missing from the panel (Intel, Samsung and IBM) to give a full picture of the 3D supply chain, ASE’s Rich Rice directed his first comment to TSMCs Doug Yu: “I respect what TSMC is doing because it brings focus and importance to the processes needed to bring products to market.” But, he noted, there are other products, customers and foundries. “What we have is an ecosystem that is going to deliver products to our customers in the next couple years. We invite TSMC to join us, but they have a company strategy and I respect that,” said Rice, “We’ll support our portion of the ecosystem, which is backside and middle processing. We love to do assembly; we do test really well and work with customers to develop test strategies and deliver product. I think OSATS are going to play a critical role. It’s going to evolve into an ecosystem that supports a much bigger pie than we need to worry about.  From ASE standpoint, we’re pumped about what this has to offer.”

One sidebar discussion that emerged during the panel and ignited a debate on cost was prompted by a question from Georgia Tech’s Rao Tummala, who wanted to know why, if there’s such a concern about cost of silicon interposers, the industry continues to focus on wafers rather than panel formats; which as his research has shown offers up to a 10x reduction in cost to manufacture. TSMC’s Doug Yu responded that via middle TSVs takes place in the middle of front-end processing, and therefore everything has to be done in the wafer fab, where tools currently only support a wafer format. “TSMC was the first to propose interposer,” he noted. “It’s not necessary the best option, but it’s how it happened.” 

From the market research perspective, Vardaman said end user surveys about the use of interposers, and the level of interest in glass turned up a lot of questions like “How do you do this with glass? Drill the vias?” They didn’t rule it out and are interested in learning more, which is an excellent opportunity for Georgia Tech to continue to investigate the answers. But she added, the present alternative is silicon interposers. Garrou added that if the industry is intent on ramping in the 2012/2013 timeframe, then we have to go with what’s available now. However, Nowak said that TSV interposers built in a foundry environment are too expensive to put into a phone; although they are a great candidate for servers and high-end communications platforms that need high density interconnect. “The 2013 timeframe is out the window for mobile applications.” He said. “Glass may have potential out further if we can come up with a solution that takes advantage its capabilities. Panels in general provide an order of magnitude better cost structure.”  (If the technical session earlier that day devoted entirely to glass vs. silicon interposers is any indication, the work is being done to bring those possibilities to bear.)

“People keep saying the cost is too high,” commented Yu (TSMC) “But for high performance applications, using TSV can save money in other ways. We can partition SOC, make bigger die smaller, which significantly reduces chip cost portion. It will become even more significant when we can scale further down.”  He added that using TSV interposers can simplify substrate and board design, which also offers huge savings. “TSMC wants to drive cost down based on existing process nodes. It will start in high-end applications and then go to main stream.”  

Clearly, the drive is here to move forward in the 2012/2013 time frame. Meanwhile, efforts continue in technology development to find ways to further reduce costs so that the next wave of mobile applications can benefit from 3D ICs.  ~ F.v.T.

* On a side note, I had asked Scott Jewler, of Powertech, this same question earlier in the week in an email. His response was that while Elpida goes through the process, they will continue to work with them on 3D IC.  “Our JDP with Elpida and UMC is progressing on schedule and we don’t see any impact from Elpida’s situation on our plans.  We’ve also expanded our engagements extensively over the last year and are working with a number of additional semiconductor companies at this time.” he said.