I have to admit, after the first day of IMAPS Device Packaging Conference last week, I was thinking, “Well, that was a good recap of what’s been going on in 3D for the past 8 years.” Other than some ongoing process tweaking to improve yields and cost issues, I wasn’t exactly hearing anything new (at least not to me). But then I caught the undercurrent of building enthusiasm despite remaining challenges. It was a palpable hum that brewed to a full blown roar during the 3D Panel on Memory Cube Readiness on Wednesday night. (Ok, maybe I’m exaggerating – it was as much as a roar a room full of engineers can make- but trust me when I say we were all pretty much cheering on the inside.)
I liked Phil Garrou’s analogy –we’ve been pushing the ball uphill for quite some time, but now it’s over the top, rolling down and gaining momentum. He touched on events and announcements over the past year that demonstrate this momentum beginning with GlobalFoundries and Qualcomm’s collaboration announcement in March 2010, followed by TSMC plans for 3D IC design using interposer technologies in June, along with UMC/PTI/Elipida’s collaborative announcement of developing DRAM/logic stacks. Then in September, Nokia declared they’d introduce a wide I/O 3D interface in 2013 and Xilinx launched Virtex stacked silicon technology using interposers in October. Micron has been hinting that its hypercube will be launched in 12 -18 months, and Samsung has jumped on the wide I/O memory bandwagon.
We can’t say that all the challenges have been solved – they haven’t. And that cost-of-test issue is suddenly looming large. But what’s happened is that there are critical advancements needed to meet the demand for consumer product requirements that can’t be done any other way than by 3D integration, whether we’re talking about 2.5 D interposer technology or full-blown 3D IC stacking. And either way, TSVs are involved, are they not? One of the big debates is still whether interposer technology is stepping stone to full 3D, or whether it is an integral part of 3D packaging. Most argue the latter, especially when it comes to 3D heterogeneous systems.
Figuring out a new business model is still a big challenge for mixed technologies, such as identified killer app of wide I/O DRAM on logic. Nowack said it would be best if we don’t have to change business model – if we can start from POP model, with different suppliers providing memory and logic, it would be good in the interim as there is a lower risk associated for all players. Eventually, evolving to a more complex business model will be more cost efficient. Some have even suggested that returning to more vertical integration would make more sense than the fabless or ‘fablite’ model has for the past few years.
Garrou notes the customer/vendor relationship must become closer to get it done. This is evident in the collaboration formed between Elpida, UMC, and PTI, and is a model that seems to be working. He explained that the three companies put the program so they can share responsibilities equally. He also noted that it all had to start with memory, because you can’t put the memory on the logic until you have the memory.
As Peter Elnius so succinctly put it in his historical presentation comparing flip chip and WLP with the evolution of TSVs, no one will change technology until they have to. It’s human nature. It’s only natural for technology suppliers to resist changes that could pose a threat to existing infrastructure and jobs. Therefore, current technology is usually extended to its limits before anything new will be implemented. Ultimately, the decision rests on the shoulders of the IC product manager, who must be willing to risk his or her career if the new technology fails. During the Q and A of the 3D Panel, Amkor’s Lee Smith reiterated these sentiments pointing out that business logistics are critical. OEMs don’t want to pay margins. “Industry is risk averse,” he said. “No product manager wants to be the first to incorporate a new tech without knowing the yield.”
“It’s all about creating a value proposition that has some legs to it; one that can’t be met with the reigning technology.” notes Qualcomm’s Matt Nowack, talking about the company’s motivation for through silicon stacking (TSS). “Just replacing wire bond with vias is not enough of a motivator. It’s the opportunity to develop new architectures and new software that makes TSS compelling.” During the 3D panel, Nowack said high density interconnects is the right value propositions. The ability to make thousands of connections between chips can’t be emulated with wire bond.
So how close are we? For Qualcomm’s part, Nowack reports that the company is building test vehicles —TSS integrated Demonstrators —working on yield improvement and reliability testing. Companies are installing equipment for manufacturing and bring up technology. Amkor’s Ron Hoemueller reports that the company is “actively engaged in programs that will require qualification by end of this year.” He said memory suppliers are ready to ship products in stacked cube formats. “At this point, the momentum is there. We don’t see it as risk-adverse.” He noted. “The path is set; ball is rolling and is going to happen.” See that? There’s that ball rolling analogy again, and it’s clearly picking up speed. ~ F.v.T.