CEA-Leti has announced a multi-partner project to demonstrate high-alignment-accuracy (<1µm) chip-to-wafer structures made by direct metallic bonding. Such structures are required for high-performance 3D integrated circuits and could enable a wide range of applications in microelectronics as well as in optoelectronics or MEMS.
Leti has acquired a customized 300mm FC300 pick-and-place tool from SET, Smart Equipment Technology, to demonstrate the technology.
The customized system will be used by the Minalogic PROCEED project. Minalogic is the global competitive cluster specialized in micro- and nanotechnologies and embedded intelligence. In addition to Leti and SET, partners are STMicroelectronics, ALES and the CNRS-CEMES. The PROCEED Minalogic project is a 4.2 million-euro, 24-month project that began in December 2009 and is supported by French FIU (Fond Interministeriel Unique).
The chip-to-wafer direct-metallic-bonding technology was developed at Leti to break through certain 3D-integration limitations. For example, the technology allows chips to be attached to a substrate at low temperature and with low bonding pressure. This technology also allows interconnecting the chip and the substrate electrically through local metallic bonding.
“This collaboration puts Leti in a very good worldwide position for 3D-technologies development,” said Leti CEO Laurent Malier. “We will identify the key challenges of 3D product engineering, and chip-to-wafer strategy with direct-metallic bonding is a very promising option for overcoming those challenges.”
The equipment was developed by SET based on its high placement accuracy FC300 system to adapt it to direct-metallic-bonding requirements.
“SET is proud to be leading the Minalogic project, PROCEED, in collaboration with STMicroelectronics, CEA-Leti, ALES and the CNRS-CEMES,” said Gaël Schmidt, managing director of SET. “It provides cutting-edge equipment solutions enabling the CEA-Leti process integration. SET has a strong interest for this non-thermocompression metal-to-metal bonding, which may be a key to throughput improvement required for the adoption of 3D-IC integration.”