Amy News
Cost Comparison of Fan-out Wafer Level Packaging and Flip Chip Packaging
In recent years, there has been an increased focus on fan-out wafer level packaging. While fan-out wafer level packaging may...
Opportunities for 2.5D and 3D Cost Reduction
A little over a year ago, I wrote a Knowledge Portal entry about the cost of 3D ICs. Here I... Cost Analysis of a Wet Etch TSV Reveal Process
Through silicon via (TSV) technology is a key design element being incorporated into more and more advanced packaging designs today....
Wafer-to-Wafer Bonding Cost Analysis
Last year, I did an analysis that included the topic of wafer-to-wafer bonding. Specifically, it was a comparison of the...
Finding the Right Time and Place for 3D ICs
As a cost modeling company, when we were asked to speak at 3D ASIP this past December, the initial topic...
