The adoption of 3D ICs allowed the elimination of the “Memory Wall” using a new memory architecture and through silicon via (TSV) technology. While individual ICs became faster with each process node, the communication between the chips was constrained by limited pin counts, power hungry I/Os, and PCB-space limitations. Assembly of multiple dies into one package enables extremely wide busses between them, shortens latency, and expands bandwidth between logic and memory while cutting the power dissipation by up to two orders of magnitude.
The large memory vendors Micron (including Elpida), SK Hynix, and Samsung) as well as the specialty memory house Tezzaron, recognized this opportunity and already introduced DRAM “memory cubes.” Combining multiple dies in one high pin count package or die stack, they offer very large memory capacity. By mounting such a cube on an interposer, side-by-side with a logic die or making them part of a 3D IC vertical stack, the “memory wall” has been effectively eliminated.
High bandwidth memory (HBM) is one of the most important 3D IC developments in the last 10 years. over the last decade, stacked DRAM with TSVs has transitioned from a handful of research programs to rapidly increasing volumes.
Tezzaron has provided small quantities of 3D ICs for high-speed memory applications since 2005. Micron, Samsung, and SK Hynix began producing DRAM stacks with TSVs in late 2014 and early 2015 (Figure 1)
Micron began shipments of its Hybrid Memory Cube (HMC) in 2015. DRAMs and the logic controller were interconnected with TSVs. HMC was packaged in a ball-grid array (BGA) and tested before assembly on the board. The HMC is used in Intel’s Knights Landing. The silicon-on-insulator (SOI) logic layer was fabricated by GLOBALFOUNDRIES (which purchased IBM’s fab) and the memory was fabricated by Micron. Micron used a thermo-compression bond (TCB) process with a non-conductive film (NCF) underfill for its die stacking in the HMC.
