Plus: TSMC Packaging in AZ; Deca/Microchip/SST Non-volatile Memory Packaging
Taiwans Minister of Economic Affairs reports that he received information about a possible US government investment in TSMC.
If the US were to invest in TSMC, the plan would need to be reviewed by the Taiwan Department of Investment Review.
Kuo’s remarks came after US Secretary of Commerce Howard Lutnick said that the U.S. government is looking into the federal government taking equity stakes in computer chip manufacturers that receive CHIPS and Science Act funding to build factories in the country, Reuters reported, citing two sources.
After agreeing to take a 10% stake in Intel in return for their $10B in Federal Chips Act grant monies for building new semiconductor fabs in the United States, the U.S. government appears to be looking for similar arrangements with other recipients of CHIPS Act monies. Reports are that the US is now exploring how the US can receive equity stakes in exchange for CHIPS Act funding for companies such as TSMC, Samsung and Micron.
The commerce department oversees the $52.7B CHIPS Act, which provides funding for research and grants for building chipmaking facilities in the US. The commerce department late last year finalized subsidies of $6.6B for TSMC, $4.75B for Samsung and $6.2B for Micron to produce semiconductors in the US.
TSMC Speeding up Arizona Packaging Facilities
According to the Commercial Times of Taiwan, TSMC is pressing ahead with its U.S. expansion with site preparation underway for its two advanced packaging plants (AP1, AP2) in Arizona, with construction set to begin in 2H26 and production by 2028.
Reportedly, AP1 will focus on expanding System-on-Integrated-Chips (SoIC) and Chip on Wafer (CoW) technologies, while AP2 will specialize in Chip-on-Panel-on-Substrate (CoPoS) to meet local demand for AI and HPC chip packaging. TSMC’s U.S. facilities will initially center on SoIC and CoW, while the back-end on-Substrate (oS) stage will be handled by Amkor Technology.
SoIC represents TSMC’s most advanced packaging technology currently in volume production and will be integrated with CoWoS and eventually CoPoS. The report adds that beyond AMD, Apple, NVIDIA, and Broadcom are also expected to adopt SoIC for their high-end products.
Reports indicate that SoIC will likely be adopted in Apple’s next-generation M-series chips and that AMD’s next-generation EPYC processor, Venice, is expected to use TSMC’s 2nm process paired with SoIC packaging.
Meanwhile, NVIDIA’s upcoming Rubin platform, set to debut next year, will also adopt SoIC technology. According to the report, Rubin’s GPU and I/O dies will be manufactured separately—with GPUs produced on N3P and I/O on N5B—then integrated through SoIC to combine two GPUs with one I/O die.
Deca and Microchip / Silicon Storage Technology (SST) Announce Strategic Collaboration to Enable NVM Chiplet Solutions
Deca Technologies and Silicon Storage Technology (SST), a subsidiary of Microchip Technology, have announced a strategic agreement to develop a non-volatile memory (NVM) chiplet multi-die package.
This collaboration combines Deca’s M-Series fan-out and Adaptive Patterning technologies with SST’s industry-leading SuperFlash embedded flash technology. The companies are offering customers to design, verify and commercialize NVM chiplets which offers technical and commercial advantages over traditional monolithic integration.
The collaborative solution provides a modular, memory-centric foundation for advanced multi-die architectures by combining the strengths of both companies. The chiplet package leverages SST’s SuperFlash technology, along with the interface logic and physical design elements required to function as a self-contained chiplet. This is paired with Adaptive Patterning-based redistribution layer (RDL) design rules, simulation flows, test strategies and manufacturing paths through Deca’s ecosystem of qualified partners.
Deca and SST will jointly support customers from early design through qualification and prototype manufacturing. The companies aim to enable broader adoption of heterogeneous integration, engaging with customers globally to bring chiplet solutions to market.
DECA / SST noted that “Chiplet technology enables designers to go beyond traditional scaling to deliver enhanced functionality and performance and get products to market faster. Chiplets allow the reuse of existing IP and can facilitate the mixing of advanced process nodes with less expensive legacy geometries. By utilizing the most appropriate die technology for a particular function, chiplets provide a versatile, efficient and economical pathway for advanced semiconductor innovation.”
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