In the August issue of IEEE Spectrum magazine, Samuel Moore published an article entitled “The Node is Nonsense”. (Note: Samuel Moore not Gordon Moore) Let’s take a closer look at what Moore is trying to tell us and see how advanced packaging fits in.

Where the Node Came From

Back when Gordon Moore first pointed out the trend that carries his name, about 50 transistors were being integrated on an IC and there was no such concept as a node. Today, processors are being fabricated at the 5nm node and we are told to expect the 1nm node (the width of 5 silicon atoms) within a decade.

But…this article correctly points out that the picture the semiconductor technology node system has portrayed has been misleading for at least 2 decades. For instance, most of the critical features of a 7-nm transistor are actually considerably larger than 7 nm. Samuel Moore contends that continuing to focus on “nodes” obscures the fact that there are actually achievable ways semiconductor technology will continue to drive computing forward even after CMOS transistor geometry ceases to shrink.

Since 1971, the linear dimensions of a MOS transistor have shrunk down by a factor of roughly 1K and the number of transistors on a single chip has increased 15MM. The metrics used to gauge this progress in integration density have been dimensions called the metal half-pitch and gate length. These are defined below.

  • Metal half-pitch is half the distance from the start of one metal interconnect to the start of the next on a chip.
  • In the planar transistor design, gate length measures the space between the transistor’s source and drain electrodes.
 Node determined by metal half-pitch and gate length

Figure 1: Node determined by metal half-pitch and gate length.

In that space sits the device’s gate stack, which controls the flow of electrons between the source and drain. It has been the most important dimension for determining transistor performance because a shorter gate length suggested a faster-switching device.

For a long time, these dimensions were roughly equivalent and became known as the “node”. These features on the chip were typically made 30 percent smaller with each successive generation. Such a reduction enabled the doubling of transistor density because reducing both the x and y dimensions of a rectangle by 30 percent means a halving in area. Presto, we got Moore’s Law!

Using the gate length and half-pitch as the “node number” served its purpose from the 1970s through the mid-1990s, but then the two features began to uncouple. Chipmakers began to shrink the gate length more aggressively than the other features. For example, transistors made using the so-called 130nm node actually had 70nm gates. The result was the continuation of the Moore’s Law density-doubling pathway, but with a disproportionately shrinking gate length. Yet industry, for the most part, stuck to the old node-naming convention.

In the early 2000s, other processes were devised to increase performance. For instance, the industry put part of the transistor’s silicon under strain, increasing the speed and power efficiency of CMOS devices without making the gate length much smaller.
By 2011, at the “22nm node”, Intel switched to the FinFET transistor architecture. The devices had 26-nm gate lengths, a 40-nm half-pitch, and 8-nm-wide fins. Thus at the 22 node, the original concept of “node” had absolutely no meaning, “…because it had nothing to do with any dimension that you could find on the die…”

Time to Rename the Node?

Thus, Moore and many others contend we need a better way to describe the technology that we have developed/are developing. The nomenclature should reflect the sizes of actual features important to the transistor. One suggestion has been to use measures that describe the real limit on the area needed to make a transistor:

  1. The contacted gate pitch (G), i.e the minimum distance from one transistor’s gate to another’s;
  2. The metal pitch (M), which measures the minimum distance between two horizontal interconnects;
  3. The number of tiers of devices on the chip (T) since we are quickly approaching the time when further shrinkage is impossible, and the only way forward is to stack.

The coming 5nm chips will have a contacted gate pitch of 48 nm, a metal pitch of 36 nm, and a single-tier thus making the GMT metric G48M36T1.

For silicon, CMOS multi-tier is still in the lab for now. For more than a decade, industrial researchers have been exploring ways to produce so-called “monolithic 3D ICs,” chips where layers of transistors are built atop one another. It hasn’t been easy, because silicon-processing temperatures are usually so high that building one layer can damage another. Several research institutes such as IMEC and CEA Leti are developing technology that would build the two types of transistors in CMOS logic-NMOS and PMOS-one on top of the other, but commercialization appears a ways off.

LMC instead of node

Figure 2: New nomenclature based on the density of logic, memory, and interconnects.

An alternative to the GMT metric is being developed by a number of prominent EE professors from Berkley and Stanford called LMC. They wanted a metric that took into account not just the processor but also other key performance-impacting aspects of the entire computer system. LMC describes the density of logic (L), the density of main memory (M), and the density of the interconnects linking them (C). The figure below shows how these have changed over the past 40 years. As they state it “…at its most basic, a computer is just that: logic, memory, and the connections between them”.

They contend that improvements in DL, DM, and Dc are the prime contributions to the overall speed and energy efficiency of computing systems. They have plotted historical data showing a correlation between the growth in logic, memory, and connectivity that suggests a balanced increase of DL, DM, and Dc has been going on for decades (Figure 2).

In the LMC metric, DL is the density of logic transistors, in the number of devices per square millimeter. DM is the density of a system’s main memory in memory cells per square millimeter. And DC is the connections between logic and main memory, in interconnects per square millimeter.

In conclusion, while the debate is ongoing over how best to describe the future of scaling, it is clear that the time is long gone when a single number can be used to describe how advanced a semiconductor node is. Something more descriptive than the currently erroneous “node “ numbers is required.

The position of IFTLE is that it is also clear that only TSMC, Intel and Samsung are really focused on continued scaling. With the rest of the industry adopting a co-design approach including the appropriate “node” chip with the appropriate advanced packaging solution, maybe the LMC approach is more appealing long term.

For all the latest in Advanced Packaging stay linked to IFTLE………………….

Phil Garrou

Dr. Philip Garrou is a subject matter expert for DARPA and runs his consulting company…

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