Herb Reiter

After more than 20 years in technical and business roles at semiconductor and EDA companies, Herb Reiter founded eda2asic Consulting, Inc. in 2002 to focus on increasing the cooperation between…

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On Thursday and Friday of last week, Monterey, California’s previous state capital, became the center of presentations and discussions about IC design challenges as well as latest innovations / progress made in the field of EDA tools and IC design methodologies at Electronic Design Process Symposium (EDPS) 2015.

We also learned a lot about FinFETs and FD-SOI during Thursday morning’s keynote, presented by Oracle’s Tom Dillinger, followed by two hours of sparring between advocates for these two camps. The afternoon started with an update on interposer-based and vertically-stacked multi-die ICs, followed by a session about Hybrid Virtual Prototyping. The dinner keynote by Qualcomm’s Dileep Bhandarkar looked back almost 50 years and outlined important milestones in the history of microprocessors.

Just like in many previous years (to be exact, EDPS was held every year since 1993), the second day focused on one important topic. This year’s center of attention on Friday was Low Power Design, Standards and Evolution. Several EDA tools and IC design experts presented and discussed how to reduce IC power dissipation. Friday’s highlight was Professor Andrew Kahng’s keynote. He showed us a roadmap for low-power design, gave us an overview of his contributions to the ITRS and demonstrated what his students at UC San Diego can learn.

Monterey is about 1 hour and 15 minutes south of Silicon Valley. Far enough to get you away from your daily hectic and routine. We met again at the Monterey Beach Resort, a few miles north of downtown. The usual breakfast buffets, lunches and Thursday’s dinner are great networking opportunities to get to know most of the typically relatively small audience of 60 to 80 attendees and presenters, outline your areas of interest and raise 1 on 1 questions.

After a brief welcome by the conference chair, Cadence’s Aparna Dey, Tom Dillinger’s keynote addressed an important question: “Should I use FinFET technology or fully depleted SOI for my next design?” Dillinger highlighted the key characteristics of both, compared the benefits of fins in bulk-CMOS, their availability in 16/14nm device features with the currently available 28nm planar transistors in FD-SOI and explained the tradeoffs to consider.

In spite of similar performance versus power, most designers choose 16/14 nm FinFETs over 28 nm FD-SOI today, because these FinFET technologies enjoy a strong ecosystem support. EDA tools, libraries and IP, as well as broader manufacturing support speak for FinFETs. However, when using FinFETs, designers complain about the modeling- and design complexities of fins, the need for double pattering (coloring), the higher mask cost and added variability the extra masking step introduces. If 10nm FinFETs will demand triple or even quadruple patterning, they may face a significant disadvantage, compared to the 14nm FD-SOI technology, currently in development. This triggered a heated discussion during the panel Dillinger moderated right after his keynote. Samsung’s Kelvin Low, Stanford’s Boris Murmann, Synapse’s Marco Brambilla and Globalfoundries’ Jamie Schaeffer responded to many questions from the audience. Factors speaking for the use of FD-SOI were lower device parasitics, simpler modeling, back-biasing ability, a simpler IC manufacturing process and fewer masks as well as several other factors, while the higher cost of substrates (=blank wafers) and the weaker ecosystem support spoke against FD-SOI.

The afternoon started with a presentation by this author about the expanding ecosystem and the broader use of interposers and vertically stacked dice in multi-die ICs, serving many different applications. Figure 1 lists a number of publicly announced multi-die projects.

EDPS1 Figure 2 gives an overview of a die-package CO-design flow that this author is promoting.

EDPS2

Similar to what the silicon manufacturers established in the 1990s with process design kits (PDKs), the assembly and test houses should consider automating the characterization, modeling and encrypted data transfer of their capabilities to IC and package designers. This will simplify providing timely and accurate inputs to the design tools for single- and multi-die ICs. An assembly design kit (ADK) will help IC- and package designers to walk the fine line between costly over-designs – that will lose money – and unreliable under-designs – that will make companies lose customers. ADKs will make it easier to meet specifications and to achieve cost-effective and reliable designs.

Cadence’ Brandon Wang updated the audience on 3D-IC Designs for Power, Performance and Cost. He presented Cadence’ range of EDA tools for die, package and PCB design, showed how Cadence supports TSMC’s low-cost InFO wafer-level packaging technology and projected further progress towards higher performance at lower power, e.g. with monolithic 3D IC technology.

Mentor’s Dusan Petranovic focused his talk on the need for modeling and design of 3D-IC stacks, especially of the interaction between individual dice, TSVs, and micro-bumps. Accurate parameter extraction and exhaustive verification – within the proven Calibre environment – are essential for a design project’s success. Petranovic also showed how Mentor supports TSMC’s InFO packaging.

Last, but not least, ASE’s Rich Rice spoke about the company’s manufacturing experience with multi-die ICs and activities assembling a broad range of devices, modules and systems. Rice explained different business models, emphasized their alliance with Inotera to manufacture interposers and other manufacturing steps performed at partners, to complement ASE’s in-house efforts. He showed that wafer-probe and test are still challenging, while all other manufacturing steps are well understood and high yielding. Like this author did, Rice also highlighted the benefits of accurate modeling and validation.

The next session focused on Hybrid Virtual Platforms, to reduce IC design times and to minimize bugs. While speakers from Mentor and Cadence outlined their companies’ solutions for pre-silicon verification, Nvidia and Intel representatives presented how they utilize hardware emulators and software tools in conjunction to exhaustively verify their complex designs before tape-out.

After dinner at the Monterey Yacht Club, Qualcomm’s Dileep Bhandarkar shared with us his many years of experience in design and management of microprocessors. His presentation started in 1971. The 4004 microprocessor at that time was comprised of 2300 ten micrometer transistors, while the near future will bring us processors with tens of billions of five nanometer transistors.

Friday, the Low Power day, started with a keynote from Jim Kardach, a former Intel executive. He outlined Intel’s approach to power reduction through several decades, working on the processor, peripherals, communication standards and software.

Cadence’ Steve Carlson, Synopsys’ Pat Sheridan, Atrenta’s Bernard Murphy and eSilicon’s Prasad Subramanien shared with us a wide range of flows and methodologies how to reduce power consumption of IC designs. While C x V2 x F was in the center of every talk, the need for lowering supply voltages, for both logic and memories, dominated.

Professor Andrew Kahng’s keynote complemented the low-power experts’ talks with a very impressive, wide-ranging list of trends, currently possible power-reduction design methods, process technology considerations, application requirements and likely developments in future.

Please join us next April for EDPS 2016, to present your know-how and/or meet experts and learn. ~ Herb

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