Guest Blogger, Paul Werbaneth, shares his take-aways on 3D ICs at the last week’s Common Technology Platform

far-side-what-dogs-hear-243x300There was little advance promotion of 3D IC topics at the well-promoted Common Platform Tech Forum 2013 event, held this year at the Santa Clara (CA) Convention Center on Tuesday 05 February 2013, but I figured that, just like Gary Larson’s famous dog Ginger, my selective hearing on 3D IC topics would allow me to pick up what was said about 3D IC amidst all the other information being offered for general consumption.

The Common Platform Technology Forum, hosted annually by CP partners IBM, Samsung Electronics, and GLOBALFOUNDRIES, addresses the most demanding IC design and manufacturing challenges. This year, something like 1,700 registered attendees showed up for all or part of the full-day program, eager to hear a solid line-up of speakers promoting recent accomplishments and near-term roadmaps from the CP Alliance partners and from members of the CP ecosystem. Key event highlights included:

  • Leading-edge process technologies at 32/28-, 20-, 14-nanometer, and beyond
  • Advanced innovations such as FinFet, design and technology co-optimization, and double patterning
  • A peek into the future of next-generation device innovations being researched such as silicon nanowires, carbon nanotubes, and 3D device structures
  • A showcase of CP’s ecosystem partners and Common Platform design, enablement, and implementation offerings
  • And, visionary keynotes by IBM, Samsung, GLOBALFOUNDRIES, and ARM.

Personally, I was curious to hear just how many mentions 3D IC would garner during the day, despite 3D IC having received no advance billing in the event teaser, and I was also hoping to witness live whatever other fresh news, 3D IC or otherwise, was going to be revealed by keynote visionaries, either deliberately, in prepared remarks, or on the fly during the Press / Analyst luncheon.

Readers may recall the big news drop from the Common Platform Tech Forum in 2011 was the Common Partners’ switch from gate-first to gate-last processing in the move from the 32nm/28nm process node (gate-first) to 22nm/20nm, architected and fabricated gate-last. Surprise!  (I think more than a few people were in 2011.)

A promising start: shortly into Bruce Kleinman’s (GLOBALFOUNDRIES’ VP of Product Marketing) opening words as MC, the tagline “3D Device Structures” floated overhead as one of the rotating call-outs in the video background accompanying Bruce’s remarks.

3D IC was front-and-center right out of the gate.  With energizing music no less; Bruce took the stage to the sounds of Brimful of Asha, by the band Cornershop.  (At least that’s what I think it was.  Catchy hook that.)

Jump to the second keynote talk of the morning, by Gary Patton, PhD, VP, Semiconductor Research & Development Center, IBM): “We’re at a technology discontinuity,” commented Patton about the chip industry today. Other examples of industry discontinuities include when the industry reached the gate oxide limit (and went to HKMG),  when we reached the planar device limit (and went to FinFET), the coming limit with 3D device structures and ultimately, the atomic structure limit, which Dr. Patton sees as a future disruptor sometime after the year 2020.

As a sidebar, Patton gave a shout-out acknowledging how 3D chip stacking gives the 3D Device Structure Era continued forward momentum while the industry deals with difficult photolithography issues, particularly the long-promised yet-to-be-realized delivery of commercial EUV lithography. 3D IC is looking like a hero at this forum compared to what’s being said about EUV.

The division of labor amongst the Common Platform Alliance partners has traditionally been to have IBM contribute leading-edge semiconductor research activities (in Albany and at the Watson, Almaden, and Zurich research centers), then perform a handoff to IBM Fishkill for process refinement, and from there, to full-scale commercial device production; commercial production being the charter for Alliance Partners Samsung and GLOBALFOUNDRIES in Korea, Austin, Malta, and Dresden.

GlobalFoundries, Fab 8, Malta NY (courtesy of GlobalFoundries)
GlobalFoundries, Fab 8, Malta NY (courtesy of GlobalFoundries)

So if 3D chip stacking is a key technology in the era of 3D device structures, what’s the 3D IC supply chain look like for the Alliance Partners?  Per Mike Noonen, Executive Vice President, Global Sales, Marketing, Quality and Design, GLOBALFOUNDRIES, it’s commercial 2.5D and 3D IC production at GLOBALFOUNDRIES’ Fab 8 (Malta, NY) for 20nm and beyond process node technologies, working together with GloFo’s partners ASE and Amkor. I like how that sounds.

And I would like to have my own fireside chat sometime with Handel Jones, Owner and CEO, International Business Strategies, Inc.  Maybe it was something about the fireside chat format (no, no actual fire, just two guys conversing, sitting in comfortable chairs facing the assembled audience), or maybe it was something about the way Brian Fuller, Journalist, EE Times, coaxed the conversation along, or maybe it was the brilliant observations offered by Dr. Jones; whatever it was, I was impressed. And not just because Dr. Jones said he sees “TSV adding value to the foundry business in future.”

It’s only fair at this point for my selective 3D IC hearing to broaden to include some of the other technologies on-stage at the Tech Forum 2013.  Chief among these is EUV lithography.  Ah, EUV – you are said to still be a physics problem waiting a solution (Gary Patton, captured in the Wall Street Journal piece ”Long-awaited Tool For Making Chips Not Close, IBM Says”).

Not the kind of lithography workhorse everyone was hoping to yoke by at least the 14nm FinFET harvest, if not put to work during harvests long before.

Double Patterning, your star is ascending and you are shining ever brighter. So many mentions of you by the Alliance partners and by members of the Alliance ecosystem; everything said about you was positive – looks like you are the go-to lithography from now until about the 7nm process node; you and your teammate Triple Patterning. And what a team! Haven’t they always said don’t bet against optical lithography?

And 28nm process node, long may you run.  Samsung’s Dr. KH Kim, Executive Vice President Foundry Business, Samsung, said “We believe 28nm will be a very long node.”

I also heard about silicon nanowires and carbon nanotubes, but I like to think that, as Dr. Jones said, 3D IC will have been adding solid value to the foundry business long before 3D IC technology is disrupted once the atomic structure limit is reached.

3D IC may end up hanging around even after that too, if the money’s right. From Petaluma, CA, thanks for reading. ~ PFW







Paul Werbaneth

Paul Werbaneth is a long-time Contributing Editor at 3D InCites. Since entering the semiconductor industry…

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