Guten Tag! It’s Friday already? I’m not sure where that week went, but I managed to gather some interesting 3D tidbits throughout the course of it. Let’s begin with Sally Adee’s 3D coverage of IEEE’s International Solid-State Circuits Conference that took place in San Francisco this week.
It seems the big news was progress in 3D integration using TSV for all types of memory; right on schedule with Yole Développment’s predictions of TSV chip stacking for DRAM beginning in 2009 and ramping to high-growth in the 2010-2013 time-frame. Toshiba reportedly won the prize for having the first available product with its 3D stacked image sensor. Additionally, Infineon reported success in developing their second-generation wireless pressure sensor interconnected with TSVs on two levels of the 4-layer chip stack: the MEMS sensor and the transceiver.
I was excited to see the announcement of Tessera’s licensing of it µPILR technology to Kinsus, because I’ve been following the progress of the technology since I first saw Vern Solberg’s presentation at IMAPS in San Diego in 2006. The process calls for stacking logic, memory, flash and DRAM with low-profile, pin-shaped contacts, replacing traditional interconnects such as solder balls on semiconductor packages The plan is for Kinsus, a Korean-based package substrate manufacturer to make and sell substrates base on µPILR technology. It’s always cool to see the baby bird find its wings and take off.
There was also some buzz about 3D chip stacking equipment in development. From the Netherlands and Austria, came TNO’s announcement of collaboration with Besi/Datacon to develop a production-level die bonder for 3D chips stacking for TSV manufacturing based on Datacon’s successful 8800 flip chip bonder. The targets chip-to-wafer processes with the intention of developing a machine that starts out with processed wafers without vias and finishes with complete die stacks.
Not far away in Switzerland, Kulicke & Soffa/Alphasem is getting ready for the SEMICON China launch of its new high-production die bonder for 3D chip stacking. According to Richard Boulanger of K & S/Alphasem, the company’s tool will focus on high-performance stacked die applications first but will extend in other markets later.
There’s a lot more to both these stories, and I still have lots of questions that need to be answered, so look forward to more on these developments next week since the work day is already over in Europe. Schonen Wochenende!