I ask you, could there be a better place to host a conference dedicated to micro and nano electronics than Disney World, the place where all things are possible? This year’s event boasted the greatest turnout so far, (over 1000 attendees) and had such an abundance of papers that the committees could be highly selective in the ones they chose, ensuring a ‘cream of the crop’ technical agenda, between the professional courses, keynotes, plenary talks and technical sessions.

I pulled in to town just in time for the first panel session, “Spotlight on China”.  I have to admit, I was hoping for a lot more of the ‘inside scoop’, unfortunately, the presentations were fairly broad in scope, briefly outlining R&D, Academia, and industry presence and involvement in China. Probably the most interesting take-aways for me was from the first speaker, C.E. (Ed) Pausa, PwC, who explained that although China has become the dominating consumer of semiconductors, with consumption growth outpacing the rest of the world (29% CAGR vs 4% CAGR) there is some concern with the IC consumption vs. production gap.  In 2010 there was an 85.5B difference between value of semiconductors consumed vs. produced in China. There is motivation for the Chinese government to increase indigenous production, which in turn can mean both opportunity and challenges for established multinational companies.

As is usual, I spent a considerable part of the week sitting in on sessions that had anything to do with 3D (3D integration, TSV, interposer, etc), which were abundant this year, and covering all areas from emerging processes, materials, interconnects,  manufacturing aspects, TSV design and modeling, interposers, and more.  Many of the papers came from academia and R&D, addressing some of the still remaining challenges of 3D ICs such as C2W and W2W stacking, thin wafer handling, inspection, metrology, and reliability testing.

Chip to Wafer (C2W) was a hot item, with several presentations suggesting better ways to speed up the processes while maintaining alignment accuracy. Qianwen Chen, of Tsinghua University, presented one method that relied on well-controlled template alignment and wafer-level bonding to enable precise alignment and fewer thermal cycles resulting in high throughput. Experiments were conducted on 200mm wafers. The approach seems promising, (or so I was told) but I wonder how it will transfer to 300mm? Anyone venture a guess?  Another presentation on C2W from Chau-Jie Zhan of ITRI focused on a flux-free bonding process for 30µm pitch lead-free solder micro bumps. plasma cleaning replaces flux, and reliability reports suggest a 90% yield. In wafer-to-wafer (W2W) advancements, Pang of A*STAR presented recently developed fine pitch Cu-Cu bonding process using a self aligning monolayer (SAM) passivation prior to bonding that is said to optimize Cu-Cu contact resistance and provide thermal stability and reliability.

There were several papers that addressed thin wafer handling, including one presented by Eric Beyne, of imec, that demonstrated integration of TSVs with extreme wafer thinning and backside processing on a 300mm production line and also evaluated the compatibility of thin wafer handling with backside processing. Likewise, A*STAR introduced a novel backside via revealing and passivation integration process involving Si/Cu CMP to overcome limitations that affect uniformity the traditional blind thinning process is used. ITRI chimed in with a paper on process integration and reliability testing for high aspect ratio, super filled vias, using a thin wafer handling technology with thermal plastic material. According to the study, this slide off method allowed for processing of a <50μm, 200mm wafer.

In addition to process papers, it was gratifying to see so much work taking place on metrology, reliability, characterization, design, modeling and thermal management, evidenced by a numerous papers on these topics. This is just another sign of 3D becoming near term rather than emerging.

Papers focused on TSV interposers were so abundant, two sessions were dedicated solely to them. Suffice it to say that the industry has found its first step to 3D integration, and everything from 3D systems, new generations of package on package (POP), 3D system-in-package, and memory on logic stacks are being enabled by them.

Needless to say, with so much to follow, I didn’t really take advantage of Disney attractions, save for a few strolls down the Boardwalk to watch the fireworks and relax with friends and colleagues over drinks and dinner. ECTC came through with a great evening Gala complete with open bar, lots of yummy food and the biggest pan of Paella I’ve ever seen. Next year, the festivities move to San Diego, and abstracts are already being accepted. Submit your 750 word abstracts to www.ectc.net by October 10, 2011.

Francoise von Trapp

They call me the “Queen of 3D” because I have been following the course of…

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