Extending Legacy Technologies into the 3D Space

While TSVs technologies make their way out of R&D on to the manufacturing floor, improvements and developments in non-TSV 3D packaging approaches continue to make waves in the industry. It only stands to reason that for companies already involved in high-volume manufacturing either as a supplier, packaging foundry, or licensor of legacy technology, that improvements affecting existing 3D package configurations have a higher and more immediate return on investment.

DEK waferTake DEK, for example. The company is always on the lookout for new applications to extend their core competency screen printing platform. By tightening their ball placement pitch processes to accommodate as low as 70µm pitch, they’re tools are now suited to the ball placement step for eWLB packages. Additionally, DEK’s tools play a part in the coating processes for 3D edge connection technologies.

Henkel Electronics Group and Asymtek have been collaborating to develop a material, tool and process solutions for replacing die attach film with a liquid adhesive for die stacking. They’re targeting high volume flash memory applications that targets wire bond as the method of interconnect. “Anything that takes us into the memory space is intriguing,” notes Greg Wood, VP sales and marketing for Asymtek. The company is working on a prototype tool for dispensing the adhesive while Henkel masters the chemistry. This lower cost liquid adhesive is sprayed on the wafer surface for force-free application; an attractive method of delivery for today’s ultra-thin wafers. Additionally, the formulation allows for a 5-20µm film build.

According to Doug Dixon, of Henkel, the company’s advanced researched group continues to work on material solutions for future applications (3-5 years out) including 3D technologies to the extent that they’re designing molecules. “These materials will enable and change the semiconductor industry,” he notes.

Expecting that it will take some time before TSV is ready for DRAM applications, Tessera is focusing development on next-generation of their µPilr technology, which was first introduced in 2007 as solution for thinner package-on-package (PoP) solutions. According to Craig Mitchell, this is a CSP solution that can be implemented quickly using existing materials and equipment to improve performance. While the early generation of µPilr technology targeted PoP at the second level of interconnect, this generation is a flip chip µPilr approach that replaces the solder bump from the chip to the substrate with a µPilr pin. Mitchell said the company has demonstrated this technology at 100µm pitch, and is believed to scale below that.

Hearing from those whose products serve the scope of semiconductor manufacturing is a good reminder that even if the 3D TSV roadmap is the hottest topic of discussion, it’s still just part of the solution. As Jan Vardaman pointed out in her presentation during the “Bridging the Gap “ TechXpot, on the mobile microprocessor roadmap, there is no single solution. “There is a plethora of package offerings,” she noted. “You have to pick the right one for the application.”