French research insitute, CEA-Leti and Docea Power, developers of software for power and thermal analysis at the architectural level, have entered into a common lab agreement to combine their expertise in 3D silicon integration and thermal and low-power design. CEA-Leti will use EDA tools provided by Docea Power to build 3D-IC designs and methodologies for developing advanced applications consumer and wireless.

The “More than Moore” roadmap offers opportunities as well as challenges for optimizing power consumption of new systems and securing their thermal behavior. To seize these opportunities and tackle the challenges of stacking ICs, an efficient architectural modeling solution is needed that takes into account the physical effects of heterogeneous integration, while allowing fast exploration of the design space.

The collaboration aims at improving design quality and validating a new generation of high-level design tools for 3D-IC wireless and consumer applications. “Thermal management and power-efficiency are key factors for success in nowadays designs. Through our cooperation, the thermal and low-power design Aceplorer platform from Docea Power will help to improve the overall design flow, reduce costs and improve the quality of our 3D-IC design,” said Laurent Malier CEO of CEA-Leti. “This collaboration with Docea Power will also help us build a new generation of 3D-IC for Leti and our industrial partners.”

According to Ghislain Kaiser, CEO of Docea, the company’s Aceplorer platform will enable power and thermal modeling of stacked dies, including 3D interconnect using through-silicon vias (TSVs) and re-distribution layers (RDLs) and the power distribution across multiple layers. “Collaborating in a common lab with Leti, and benefitting from its broad and deep expertise in 3D-IC technology, gives us the opportunity to validate and improve our platform for addressing the fast-growing 3D stacked-IC market,” he added.

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