Will this be the year for 3D IC design tools? Who knows for sure? But by the looks of the agendas of some upcoming design-centric events, 3D certainly seems to be on everyone’s mind.
The fun begins next week with DesignCon 2010, Feb 1-4 in Santa Clara, which has some interesting 3D focused events in its extensive program. On February 2, Exploring the Business Aspects for 3–D Device Success, will examine 3D integration from the business perspective, asking such provocative questions as: who will benefit the most from the 3–D approach? Are these the companies investing in research? If not, who pays and what’s the benefit to them? The panel, chaired by Ed Sperling, EIC, System–Level Design, comprises representatives from Synopsis, eSilicon and Mentor Graphics.
Later that day, Per Vicklund of Mentor Graphics will host a panel discussion, SiP and Advanced Packaging – A Growing Marketing Segment in an Economic Downturn – Turning to 3D Packaging. Here, a panel of users and industry experts will address the roadblocks to successful communication of the benefits of 3D, focusing on technology maturity, the question of standardization, design tool readiness, and skills required.
On February 25, MEPTEC will host full day symposium, From Chip to System, Design Challenges and Solutions, featuring keynote speaker, Tom Gregorich of Qualcomm. Well-known in the 3D circuit, Gregorich will talk about concurrent design. While techical presentations will cover the gamut of design challenges, a good percentage of the talks look specifically at those in the SiP, 3D package and TSV realms, and include such critical topics as design-for-test, bridging the gap from silicon-to-system, fast 3D EM solutions for digital system designs, and more.
Then as part of the DATE Europe 2010, from March 8-12 in Dresden, Germany, there will be a 3D Integration workshop on Friday, that will feature keynote addresses from ITRI’s Cheng-Wen Wu, National Tsing-Hua Univ., TW who will give speech titled “What We Have Learned From SOC Is What Is Driving 3D Integration”; and Jacky Seiller, of Amkor Technology, France, who will talk about “OSAT – Role as Partner in 3D Integration”. Presentations focus on bringing the design and test communities up to speed on 3D process technologies. For example, Claudio Truzzi’s team from Alchimer will discuss the plausibility of high aspect ratio vias, and what that means for designers in terms of reclaiming silicon real estate. Wrapping up the day will be a panel discussion moderated by Jerome Baron, of Yole Developpment, titled simply, “3D, A Reality?”
To compliment all these physical design events, we’ll be running several design-centric online discussions from Feb 8-12, and then Feb. 15-19. The first will be with Gene (‘Ski) Jakubowski,
Madhavan Swaminathan, Ph.D. and Bill Martin of E-system Design, a Georgia Tech spin-out focused on developing EDA tools for 3D and more specifically, a wave simulator for TSVs. The same week, we’ll chat with the organizers of the DATE 2010 Europe 3D workshop about the importance of 3D, and what the workshop will address. The second week, we’ll be talking with Ahmed Jerraya, head of design program’s at Leti, about the recently announced joint development agreement with R3Logic. So mark your calendars, and stay tuned for more details on these discussions in the coming weeks. – F.v.T