I think maybe the design community is tired of being referred to as “a limitation” just because the tools aren’t ready yet. I think they are also tired of being the scape goat. In any case, session speakers for “Taking Advantage of 3D: Rethinking Design Approaches”, at last week’s RTI 3D Architectures for Semiconductor Integration and Packaging, did a good job of setting the record straight and outlining what can be expected from the design community in the coming months that will bring the needed tools to fruition.
Eby Friedman, professor at the University of Rochester, offered his perspective as a chip designer, noting that designing for 3D will require a different approach than the one taken for design for 2D architectures. “ I think heterogeneity is going to be the dominate issue,” he noted, “because it involves Inter-die process variations, disparate technologies, and different materials.” In redefining problems for the 3D world, a two-step solution to floor planning will be required because placement routing now happens across planes. TSVs needed to be treated ac circuit cells that are placed on each plane separately. Computation complexity is something to consider,” he said. “How do you fuse all this stuff together?”
What’s needed, according to Paul Franzon, professor at North Carolina State University, is a holistic approach to creating 3D-specific systems. He urged the conference attendees to “admit their addiction” to electronics as they are built today, and commit to his 10 step program for adopting 3D integrations. The steps are outlined as follows:
- Admit your addiction
- Choose your 3D IC technology set
- Determine your supplier chain
- Architect your system to exploit 3D
- Manage partitions
- Work out how to defeat the cost “dragon”
- Determine a test strategy
- Solve power, delivery and thermal issues
- Put together a CAD strategy
- Detailed design and verification
Notice that the design steps are second-to-last and last on the list. If you listened to Frank Schellenberg, Ph.D , who monitors technology trends for EDA vendor, Mentor Graphics, and Lisa McIlrath, president and CEO of 3D EDA vendor, R3Logic, who spoke next, you’d understand why. Part of the delay with design tools, according to Schellenberg is that although 3D technologies are ready, there are too many options for designing. “Design automation means you need to figure out what you want to do then automate it. It’s a fool’s errand to design an EDA tool before there is something to simulate,” he said.
McIlrath concurs. “The roadmap is going to happens whether the EDA houses step up to the plate or not. If there’s an economic advantage to doing something a certain way, than people are going to do it, even if they have to rely on ad hoc ways to do it.” She says. At a certain point though, it gets too hard to continue using ad hoc approaches, and McIlrath says that time is now. The good news, notes McIlrath, is that over time, each year’s roadmap isn’t sliding out faster than we get to it. We’re catching up.
R3Logic, McIlrath’s company, is leading the charge, having introduced its 3D layout editor in 2008 that uses 3D scripts for 2D spreadsheets; and have 3D advanced physical design tools (2009-2010), 3D system design (2011), and 3D design-for-test Standards (2012-2013) all on its roadmap. The company’s layout editor, licensed and sold by MicroMagic, has been in use by Tezzaron Semiconductors for quite some time.
Speaking on behalf of Cadence Design Systems, Vassilios Gerousis, senior architect and technologist, talked about work the company is doing with Qualcomm to develop a 3D thermal analysis application that simulates flow for simulation of thermal issues. This method allows for interacting with the design flow and package modeling flow. This work has demonstrated that largest factors are power dissipation and distribution, thermal environment assumption.
Gerousis said that what’s needed is a thermal management tool with the ability to interact with the physical design environment and have computational speed to analyze large complex designs. In 3D stacks, the most sensitive part sets the thermal limit, and therefore must be treated as a system, with the lower power die dictating the limits. He also noted that thermal cross talk exists for any 3D stacking configuration, through silicon stack (TSS) or not. In conclusion, Gerouris notes, “thermal management is important but does not appear to be a unique show stopper for 3D TSS adoption.” Preparation, however, is required. Thermal management needs to be “engineered in.”
It’s clear the design community is making good strides. As Phil Garrou reported, in 2007 Cadence’s position was “we will develop EDA tools once it becomes clear that the market intedns on going in this direction.” Now, in 2009, Garrou reports that aMentor, Cadence and Synopsis have now bought in and are developing tools “with major customers.” It looks like the market has spoken.