According to Nikkei Asia, UMC is eyeing 6nm production, with a focus on chips for Wi-Fi, RF, Bluetooth, AI accelerators, and processors used in TVs and vehicles.
In 2017, UMC began to focus on mature process nodes rather than competing at leading-edge technologies dominated by TSMC. This allowed UMC to spend less capital. UMC has concentrated on expanding its offerings for 14 nm and older process nodes like its 22/28 nm lines and other specialty nodes, aiming for profitability in these sectors.
While a move back into 6nm production would typically require a massive capital outlay, Nikkei reports that UMC is considering expanding its partnership with Intel to help offset costs—potentially adding 6nm chips to their planned 12nm collaboration in Arizona, set to begin by 2027.
Qualcomm Contract
Qualcomm has historically relied heavily on TSMC for both manufacturing and packaging services. In Dec of 2024, UMC announced it had secured a major contract from Qualcomm for HPC applications.
Qualcomm is reportedly leveraging UMC’s wafer-on-wafer (WoW) hybrid bonding technology for advanced packaging of its next-generation HPC chips. These chips, built using TSMC’s advanced process nodes and incorporating Qualcomm’s Oryon architecture, are slated for use in a range of high-growth markets, including AI PCs, automotive electronics, and the rapidly expanding AI server market. High-Bandwidth Memory (HBM) integration is also planned.
UMC’s WoW “hybrid bonding” technology is said to offer a significant advantage by reducing signal transmission distances between chips. This approach represents a departure from traditional solder-ball connections, utilizing package-on-package (PoP) technology.
The deal centers on UMC’s interposer technology featuring 1500nF/mm² capacitors, which are matched with the capacitance required by Qualcomm’s ICs and memory. The UMC cap technology has reportedly passed Qualcomm’s electrical testing and moved into trial production. Volume production is scheduled for Q1 2026, according to Taiwan’s Economic Daily News.
When it comes to advanced packaging technologies, such as 2.5D and 3D packaging, which require multiple chips to be stacked or placed side by side, mid-layer capacitors are particularly important.
A report from Commercial Times suggests the company is considering expanding advanced packaging capacity by acquiring the TFT-LCD facility of HannStar in the Taiwan Science Park.
While UMC declined to comment on the rumor, it stated that it has already established 2.5D advanced packaging capacity in Singapore and has moved part of its process back to Taiwan. The company adds that further expansion in Taiwan remains a possibility.
Citing CFO Chi-Tung Liu they point out that UMC will no longer limit itself to traditional foundry services but will also move into high value-added areas such as advanced packaging.
The company currently possesses wafer-to-wafer bonding technology, a critical process for stacking wafers at the atomic level, widely used in 3D IC manufacturing. UMC’s production lines in Taiwan are already equipped with this capability, the report underscores.
In IFTLE 457 we detailed UMC licensing the hybrid bonding process flow from Adeia (then Xperi), who had previously acquired the technology from Ziptronix in 2016.
At the time, Xperi claimed that licensee UMC was actively scaling up the hybrid bonding technology, though not quite ready to accept customer orders. But that was 2020 and this is 5 years later. Although I have not seen it stated explicitly, I assume their WoW technology is your standard Ziptronix typical hybrid bonding technology. For those of you that are new to advanced packaging technology I have added the overall process sequence below.
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