The data traffic explosion, fueled by the Internet of Things (IoT), social media and server applications, has created a need for ever-advancing semiconductor technologies. Servers, mobile devices, IoT devices… they drive the requirements for semiconductors’ future processing and storage capacity.
But will we be able to continue traditional semiconductor scaling, as initiated by Gordon Moore? For a long time, we have lived in the ‘happy scaling’ era, where every technology node re-shrinks and redoubles the number of transistors per area, at the same cost. But for the last 10-12 years, while the number of transistors has still been doubling, device scaling has provided us with diminishing returns. We’ve seen these periods of ‘dark silicon’ before but always managed to overcome the related challenges. And yet again, the industry’s technology toolbox will provide us with new features to help manage power, performance, and area.
On the dimensional scaling side, extreme ultraviolet lithography (EUVL) is considered an important enabler for continuing Moore’s Law. At imec, we already showed that EUVL is capable of printing 7nm logic dimensions with one single exposure. At the same time, to enhance dimensional scaling, we increasingly make use of scaling boosters, such as self-aligned gate contact or buried power rail. These tricks allow a standard cell height to be reduced from 9 to 6 tracks, leading to a bit density increase and large die cost reduction – a nice example of design technology co-optimization.
FinFET technology has been the killer device for the 14 and 10nm technology nodes. But for the 7-5nm, FinFET technology can’t meet the 20% performance scaling and 40% power gain targets anymore. To go beyond 7nm will require horizontal gate-all-around nanowires, which promise better electrostatic control. In such a configuration, the drive current per footprint can be maximized by vertically stacking multiple horizontal nanowires. Vertical nanowires, although requiring a more disruptive process flow, could be the next step. Or junction-less gate-all-around nanowire FET devices, an attractive option for advanced logic, low-power circuits, and analog/RF applications. From the 2.5nm node onwards, fin/nanowire devices are expected to run out of steam and we will need to find ‘the next switch’. Promising approaches are tunnel-FETs, which can provide a 3x drive current improvement, and spin-wave majority gates.
Looking ahead, it might as well be the interconnect that will threaten further device scaling. Therefore, the back-end-of-line (BEOL) and the struggle to keep scaling the BEOL needs attention. We look at ways to extend the life of Cu, for example with liners of Ruthenium (Ru) or Cobalt (Co). In the longer term, we will probably need alternative metals, such as Co for local interconnects or vias.
And let’s not forget the interesting road that 3D integration is offering. Many advanced 3D integration and interconnect technologies have emerged, reducing the size of the electronic systems, and allowing for faster and shorter connections between its sub-circuits. These abilities have made 3D integration one of the techniques that will allow the industry to keep on the path of Moore’s Law. Several classes of 3D integration can be defined, related to the level in the interconnect hierarchy the systems are ‘cut’ into different pieces. There is the system-in-a-package and 3D stacked IC, and with advanced CMOS scaling new opportunities for 3D chip integration with even higher interconnect densities and smaller pitches arise; It’s the 3D system-on-chip approach where the SoC circuit is divided into different functional parts which are then stacked using wafer-to-wafer bonding. These partitions have varying functions and are built using different technologies and these are stacked heterogeneously with interconnect densities below 5µm. The system partitioning can be done at the global, intermediate of local wiring level. Think of processors, which evolve towards an ever increasing number of cores, enabled by the scaling towards 7 and 5nm technology nodes. And more cores need more on-chip memory. All this will result in more overall silicon area and more back-end-of-line needs, and hence, in an increasing wafer cost. One way to cope with this trend is by functional repartitioning of the processor followed by heterogeneous 3D-integration.
To conclude: Moore’s Law will continue, but not only through the conventional routes of scaling. We have moved from pure technology optimization (involving novel materials and device architectures) to design technology co-optimization (e.g. the use of scaling boosters to reduce cell height) and to system technology co-optimization. And to keep improving computing power, we are also exploring neuromorphic computing (brain-inspired computer concept), and quantum computing (which exploits the laws of quantum physics). In other words: there are plenty of creative ideas that will allow the industry to further extend semiconductor scaling…