Addressing Advanced Packaging Challenges in 2017 and Beyond

Addressing Advanced Packaging Challenges in 2017 and Beyond

guvinder-singh030916-copyAs the two-dimensional (2D) shrinking of planar circuits (on which Gordon Moore based his famous observation) has become more difficult and expensive, the semiconductor industry has had to find other ways to continue to put more computing power and speed into less volume. At the same time, consumers are demanding greater functionality that integrates a variety of interconnected circuit types. The result has been an increasing reliance on advanced packaging technologies that use fab-like processes to integrate multiple chips and to provide the increased I/O capability required by these increasingly complex systems. Advanced packaging is now an integral part of most scaling and functionality roadmaps.

By incorporating 2.5D, 3D, and wafer level chip scale packaging (WLCSP), both fan-in and fan-out technologies, manufacturers are able to meet consumer demand for miniaturization and increased functionality while reducing costs and improving performance. The common theme across the various packaging technologies is to shrink the re-distribution layer (RDL) line/space (L/S) pitch, which, in turn, requires increased sensitivity in the technologies used to control the manufacturing process.

During the IMAPS conference a few months ago, several speakers identified fan-out WLCSP as a disruptive technology for several reasons:

  • Simplification of the manufacturing process – it eliminates micro bumps, C4 bumps, through silicon via (TSV) and interposers.
  • Improved cost – For WLCSP, the absence of a substrate leads to lower cost. In processes that use substrates, they account for 35 percent of the packaging cost — a significant number.
  • Driving innovation – The technology can be used for multiple dies in package-on-package form as well as side-by-side, reducing the overall form factor required for mobile and the internet of things (IoT) applications. It also allows chip manufacturers to mix devices from advanced process nodes and mature nodes.

Prior to 2015, fan-out packaging was growing less than 10 percent per year. TSMC’s entry this year with integrated fan out (InFO) packaging has more than doubled the revenue for this technology. Several OSATs are in pilot line production with high volume manufacturing scheduled for his year. According to Yole Développement, the market is currently projected to grow at a compound annual growth rate of 50 percent from 2016 to 2020 and expected to exceed $2.5B by 2021 (figure 1).

advanced packaging challenges

Process Challenges

The fan-out packaging process can be divided into the following key steps (figure 2):

  • Wafer preparation – The process involves dicing the chips on a silicon wafer.
  • Reconstitution – Singulated chips are very precisely positioned, with space added between chips, on a “reconstituted” or carrier wafer, made of a soft molding compound that is hardened into wafer-like form.
  • Redistribution and finishing – The insulating and redistribution layers are created, and solder balls are formed on top, just as in a wafer-level chip scale package.  

Advanced packaging challenges

The idea is very simple: fab-like processes designed to work on conventional wafers to provide signal routing and I/O on the expanded surface area of the reconstructed wafer.  However, several challenges exist, including kerf chipping and cracking during singulation, warpage, die placement, and non-visual killer defects, to name a few. For this discussion, we will focus on non-visual killer defects.

Non-visual Killer Defects

To understand the challenges faced with non-visual killer defects, we will look at the polyimide layer. The polyimide (PI) and poly-benzoxazole (PBO) layers are specialty stress relief coatings used as a protective layer before the packaging or redistribution layer. PI layer lithography steps include coating, exposure, development, and curing. Underdevelopment can leave residue in the via, leading to electrical connectivity and performance issues, and ultimately resulting in package failure. This is a high-value problem because the customer is committing a known good die and the ability to detect process excursions prior to curing might permit re-work. Equally troubling, failures caused by such residues often occur in the field. To illustrate this point, figure 3 shows visual images of six pads, some of which are covered with unacceptable levels of residue.

figure-3 figure-3b

Using visual techniques these pads probably look very similar. There are two key issues – the residue is faint/transparent in white light illumination and the graininess of the metal makes detection by comparison to a “gold” standard extremely difficult. The images in figure 4 show the same pads using Rudolph’s Firefly™ system. In these images, there is a clear difference between the first three and the second three, and it is much easier to differentiate visually between a good and bad via opening. The dark vias are clear and the lighter gray vias have significant residue present in the opening.



This residue detection is made possible by our patented Clearfind™ technology that combines advanced camera sensor technology, dual in-line focus system, and fluorescent illumination. We have performed several successful application studies using Clearfind technology and have found that it can be beneficial in finding non-visual killer defects in fan-out packaging. We believe that Clearfind technology will be instrumental in helping manufacturers improve yield in their fan-out packaging processes.  ~  Gurvinder Singh, Director, Inspection Product Management, Rudolph Technologies, Inc.

  • Suk-Jin Ham

    I have a question.

    After what process step was the fluorescent images obtained? After the developement or after the curing of PI layer?
    Is it possible to differentiate visually between a good and bad via opening before the curing of the polymer layer such as PI.