Archives December 2016 - 3D InCites

Hugo Pristauz Drops the F-bomb at 3D ASIP 2016, You Won’t Believe What Happens Next!

Hugo Pristauz Drops the F-bomb at 3D ASIP 2016, You Won’t Believe What Happens Next!

Sorry everybody, but I couldn’t resist this Buzzfeed-esque title, because Besi’s Hugo Pristauz’ unprecedented use of “colorful” language to illustrate the “turbulent plane ride” of ramping thermo-compression bonding die attach to volume production just might go down in history as the most talked (and laughed) about incident at the 2016 3D Architectures for Semiconductor I... »

Happy Holidays, from 3D InCites!

Happy Holidays, from 3D InCites!

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Embedded Die: from Incubation to High Volume Production

The embedded-die-in-substrate platform has its own history and adoption scheme compared to other advanced packaging platforms, explains Yole Développement (Yole). Indeed while the first significant volume of embedded die in integrated circuit (IC) package substrates came from direct current (DC) converters in smartphones, penetration in other market segments of interest to embedded die such as au... »

IEDM 2016 Demonstrates Device Physics For The Semiconductor Industry

IEDM 2016 Demonstrates Device Physics For The Semiconductor Industry

In the past few months I have been reading a lot of depressing news about our semiconductor industry’s declining growth rates, shrinking profit margins, many consolidations, as well as many articles about why, when and how following Moore’s Law will be only justified for extremely high-volume designs. Sounds kind of depressing and worrisome for semiconductors, however, last week’s Internatio... »

High Productivity UBM/RDL Deposition by PVD for FOWLP Applications

High Productivity UBM/RDL Deposition by PVD for FOWLP Applications

Fan-out wafer level packaging (FOWLP) technology is an increasingly popular solution for obtaining high levels of device integration with a greater number of I/O contacts, at a lower cost. With FOWLP today we have the ability to embed heterogeneous devices including baseband processors, RF transceivers, and power management ICs in mold wafers, thereby enabling the latest generation of ultra-thin w... »

3D ASIP Returns Under The IMAPS Umbrella for Its 13th Edition

3D ASIP Returns Under The IMAPS Umbrella for Its 13th Edition

In less than two weeks, the 13th Annual Architectures for Semiconductor Integration and Packaging Conference (3D ASIP) kicks off at the Marriott San Francisco Airport, this year under the auspices of the International Microelectronics and Packaging Society (IMAPS). Long heralded as THE conference for 2.5D and 3D integration, the conference was created by the Tech Venture Forum at RTI International... »

Fan-out is the Most Dynamic IP Landscape in Advanced Packaging

Fan-out is the Most Dynamic IP Landscape in Advanced Packaging

In the fast-growing fan-out market showing 80% increase between 2015 and 2017[1], it is today essential to deeply understand the patent strategies of the key players. The Technology Intelligence & Intellectual Property (IP) Strategy Company, KnowMade has thoroughly investigated the fan-out packaging patent landscape and releases today the new patent landscape analysis titled Fan-Out Wafer Leve... »

SiP Impact, Smartphone Market Saturation… What is the Future of Fan-in Packaging?

SiP Impact, Smartphone Market Saturation… What is the Future of Fan-in Packaging?

Fan-in packaging has been a successful and steadily growing platform for over a decade. However, fan-in packaging should face a challenging future, announces Yole Développement (Yole), the “More than Moore” market research and strategy consulting company. Indeed, despite unchanged market drivers, Fan-In packaging is showing an uncertain future with a slowing down smartphone market and the gro... »