In less than two weeks, the 13th Annual Architectures for Semiconductor Integration and Packaging Conference (3D ASIP) kicks off at the Marriott San Francisco Airport, this year under the auspices of the International Microelectronics and Packaging Society (IMAPS).
Long heralded as THE conference for 2.5D and 3D integration, the conference was created by the Tech Venture Forum at RTI International, who ran it successfully for the first 12 years. The transfer to IMAPS seems a natural transition as 2.5D technologies and 3D integration move out of the R&D sector into commercialization. However, much of the organizing committee remains the same, with Alan Huffman, RTI International as the Technical Chair, and Phil Garrou, Microelectronic Consultants of NC as Program Chair, as well as the addition of Asian and European technical co-chairs: Mitsumasa Koyanagi, Tohoku University, and Mark Scannell CEA-Leti, respectively. This powerhouse committee ensures a technically robust program that will be well worth attending.
This year’s agenda follows a slightly different format, with two pre-conference tutorials to choose from on Tuesday morning: A session on fan-out wafer level packaging, lead by Qualcomm’s Beth Keser, or a session on electrical modeling & test strategies for 3D packages lead by Bruce Kim, City University of New York.
The full conference agenda gets underway Tuesday afternoon, with a plenary keynote on image sensor technology by Tetsuo Nomoto, Sony Semiconductor Solutions, followed by sessions on 2.5D/3D enabled applications and memory stacks and applications. Presentations include an eclectic mix of 2.5D, 3D packaging, and 3D system-on-chip (SoC) approaches, as well as opto-sensors, photonics, and a market overview on memory packaging by Yole Développement thrown in for good measure.
Wednesday’s agenda features a plenary keynote: Future Landscapes for 3D Integration: From Interposers to 3D High Density by Jean Michailos, STMicroelectronics, followed by a deep dive into image sensor technology, which has long been considered the original 3D application, and the only one currently in high volume production.
Next, we get to the heart of the heterogeneous integration matter, with plenary talks by Bill Chen, ASE on the heterogeneous integration roadmap, and Subu Iyer, who will talk about his work at UCLA developing solutions for heterogeneous SoCs.
We’ll round out the day with a session on 3D in military and aerospace applications, followed by updates from the equipment and materials suppliers.
The conference wraps up with two sessions on Thursday morning: the first focused on 2.5D and 3D Design issues, and the second; a status update on glass technology for high-density packaging.
By the looks of this jam-packed and varied agenda, the committee has left no stone unturned in what needs to be considered next in the world of 3D architectures for semiconductor integration and packaging. Get the details and register here.
Stop by the 3D InCites table to learn how you can contribute to the 3D InCites knowledge portal! Hope to see you there. ~ FvT
PS: If you haven’t reserved your room yet, it appears the cutoff has been extended and the room block is still opened. I just booked my room (Dec 1). Try this link and best of luck!