On one side of the fence, we have semiconductor device manufacturers (fabs, foundries, and OSATS) claiming to be ready to ramp 2.5D and 3D IC devices to production, saying that remaining issues can be engineered out. On the other side, we have system integrators who, while they believe 2.5D and 3D ICs are the answer to their performance and power prayers, aren’t ready to dive in head first because they still have questions that remain unanswered. The plenary talk, Packaging Influence on System Integration and Performance, which took place Wednesday night at ECTC 2014, brought system integrators and manufacturers together to explain both sides of the story.
During the Q&A portion of the panel, two of the questions that were asked of the panelists, who hailed from Cisco Systems, Microsoft, IBM Microelectronics, Ericsson Research, and Amkor tied directly to some of the interviews I had conducted during the day. One focused on design tool readiness, asking what is the missing link to 3D IC production? The second was whether are there any technical challenges without a solution?
In answer to the first question, Amkor’s Nozad Karim noted that while EDA tools are needed, the design engineers have worked around it. “It takes longer, but they find a way,” he said.
However, Jon Casey, IBM Microelectronics and Stephan Lesard, Ericsson Research, both said it would be nice to have tools that help you pre-determine where to break apart the system. Casey called these “tools to create models of predictive capability”.
“Where do you break a system apart to increase circuit density and gain performance?” he asked, adding that it should also help design for cooling and partitioning.
When Casey said, “It doesn’t exist in the industry.” I wanted to jump up and say – “It does! I just spent an hour and a half talking with Bill Martin of E-System Design about their new Sphinx 3D pathfinding tool that does JUST WHAT you’re describing!” Of course I didn’t; that would have been rude. But I’ll describe it here:
Getting the Full Picture with Pathfinding
This tool, developed specifically for pathfinding of 2.5D and 3D structures, is used before detailed implementation of design and layout so that designers can figure out what to put together to meet device constraints. Martin explained that pathfinding tools are used to create virtual test structures before turning it over to the design team.
“Pathfinding tools augment design implementation rules by determining what you can or cannot do,” he said. With this tool, customers can figure out configurations (RDL line spacing, wiring, etc.) that work. It takes the perplexity out of test structures.
“The problem with old tools is that they weren’t created for pathfinding and take 2-4 hours to create test structures,” said Martin. “This pathfinding tool can create test structures within minutes.” It can also allow you to model large portions of the design. Rather than analyzing 2 or 3 through silicon vias (TSVs), it’s important to look at all the TSVs because it may be that the worst performing via is the one most inner-assigned. It can be changed depending on power and ground, so it’s important to get the biggest picture possible.
What makes this tool different than existing design tools? Martin explained that when designing in the 3D space, you’re using cylindrical interconnects that don’t “mesh”. With planar structures, meshing works fine. Trying to mesh cylindrical structures takes a lot of memory. The algorithm that this new pathfinding tool uses can create an accurate electrical model without meshing, so it doesn’t consume any memory and structures can be analyzed faster. It only takes a single CPU to run the program.
“Before you get to the physical layout, do the pathfinding first, then engage with any tool that you want,” advised Martin. “As far as true pathfinding tools for 2.5D and 3D; we haven’t seen any on the market. This is not a retrofit of an existing tool.”
Martin took me on a detailed virtual tour around the tool interface to demonstrate its capabilities and ease-of-use. He demonstrated how comparisons can be made by first creating the “Lego blocks” of 3D. For example, whether using a silicon interposer or a glass interposer is a better option for a specific device by figuring out the constraints. “What do I do in design to get the performance required?” he explained. It can also be used to compare 2D SoC designs with 3D SoC designs.
“Pathfinding can save a huge amount of time and money in manufacturing cost,” explained Martin, adding that in one case it had saved a customer $70M. “You can use it to do hardware/software co-verification. If you create pathfinding just on interconnect to make sure it works across the full spectrum, you can make what you’re designing can actually be implemented and support the speeds you need.” Sounds to me like just what the doctor ordered.
This is the 3rd version of the tool, which has been tailored to Qualcomm’s requests, noted Martin. That’s right, there have already been two versions. So why isn’t this tool common knowledge by now? Martin says its because the company has been in stealth mode, just working directly with a few customers to develop the tool. But now they’re ready to take it to the big time.
Taking the Heat out of 3D Stacks
With regard to remaining technical challenges, next on the wish list for system integrators are solutions for thermal management. “The challenge is going to be thermal. We can get the power in, but can we cool it?” said Casey. “The history of technology is that every revolutionary change is combined with the ability to cool more efficiently. With stacking we’re going to run into limits. The thermal people are going to be busy.”
Some of them already are. I talked with Andrew Ho, of Dow Corning, who filled me on a new thermal interface material (TIM) Dow Corning has developed to address die hot spot and thermal dissipation problem. He said the company has working with development partners in the value chain, focused on unique requirements of 3D ICs; improving the thermal conductivity and lower thermal resistance of the material to better mitigate stress. “It’s a balancing act between adhesion, stress and modulus,” explained Ho.
While thermal vias can be used to dissipate heat from the hot spots up through a 3D stack, at the end it has to dissipate out of the device, explained Ho. The TIM helps at this point, mitigating the stress from the whole stack.
The TIM is introduced at the end of the process as part of the packaging, not device fabrication. One innovation was to enhance the materials adhesion to be compatible with the surface chemistry of the silicon, since it is applied to the top surface of the die before the lid is attached. The goal was to create a material with high thermal performance and also maintain reliability.
“It’s a reliability issue because of the 3D architecture. When warpage happens, the material has to expand or contract to accommodate this. This silicone material can do that,” said Ho. “It’s meant to contact with the hottest surface. In some instances it can be applied to the perimeter of the stack to dissipate heat out the sides.” Additionally, he said the it doesn’t crack or delaminate due to the silicone advantage.
Ho said the material is still in early stages of development. Dow Corning has been working with IBM to set up test protocols using IBM test vehicles. The material is customizable to customer specifications, for example, with regard to the method of application; whether it is printed or dispensed. Ho said the TIM’s rheology needs can also be addressed, as balancing adhesion, elongation, thermal stress and modulus. The material is also in evaluation at customer locations. I expect we will here more about this in the near future. ~ F.v.T.