Survey and Review of 2.5D and 3D IC Packaging Technologies

On April 9, 2014 Herb Reiter presented a 2.5D and 3D IC packaging-centric update in context with an IEEE/CPMT dinner meeting at the Biltmore Hotel in Santa Clara. About 50 silicon-, packaging-, assembly and test experts attended this 1-hour presentation. Most of them stayed for the very interactive Q & A session, that turned out be last another hour.

In his presentation, Reiter discussed “complementing” 2D silicon designs with 2.5D and 3D ICs. He presented the ITRS roadmap for heterogenous integration, and cost/complexity challenges of 2D designs. He then maked a case for 2.5D and 3D IC solutions to these issues, including a compelling value proposition of moving to a higher value packaging opportunity. The presentation included comparisons of 2.5D and 3D IC solutions, case studies of companies implementing 2.5D and 3D IC designs. He also touched on Monolithic 3D ICs. He concluded with business considerations for 2.5D and 3D ICs.

The slides are now available here on the CPMT website.