3D IC System Verification Methodology: Solutions and Challenges

By Dusan Petranovic, Member, IEEE, and, Karen Chow, Member, IEEE, (Mentor Graphics)

The three largest EDA companies are taking an evolutionary, rather than a revolutionary, approach in developing the 3D IC design tools. This appears to be a good decision because the technology, the rules and the standards are still evolving. The main EDA challenges are expected in the design space exploration [6], automatic across-die design partitioning, placement and routing, thermal and stress management, and 3D stack testing. Regardless of design style and methodology, physical 3D IC System Verification is a necessary step to accurately verify design rule compliance, 3D stack LVS checking across the die parasitic extraction and simulation. Existing verification flows include the use of DRC, LVS and extraction to verify the connectivity of multiple stacked dies [7].

At the present stage of technology development and 3D IC applications, it is assumed that there are no interactions between the TSVs, and a model for a single TSV is provided by the foundries. For verification purposes, TSVs are treated as an LVS device (GDS based flow) or as a Via (LEF/DEF based flow), and the provided TSV model is used for downstream simulation. This assumption, however, may not hold true as the technology advances and the TSV densities and frequencies become high, requiring accurate modeling and extraction of the interactions. Significant research effort has been put into this area recently [8]–[10] and it is expected to intensify in the coming years. This new methodology would require more accurate process description, accurate frequency dependent modeling and appropriate flow development to take advantage of the modeling accuracy.

We discuss various verification flows and present the solutions that allow for accurate verification of current 3D designs in this paper. We also point out the challenges that come with the new applications and identify development efforts needed to respond to those challenges.

This paper was published in 2011 by IEEE. It was submitted to 3D InCites by Mentor Graphics as supporting data for the 2013 3D InCites Awards. Download the complete paper here.