ECTC Logo 2012One thing is for sure, from special sessions to the standard technology tracks, there is no shortage of 3D-focused events at ECTC 2013, which takes place at the Cosmopolitan, in Las Vegas NV, May 28-31, 2013.

For starters, this year’s program takes on some remaining key issues for 2.5D and 3D IC manufacturing with two special sessions scheduled for Tuesday, May 28, 2013.

From 10am-12pm, join Broadcom’s Sam Karikalan leads a panel session, The Role of Wafer Foundries in Next Generation Packaging.  On the table: the need for high density TSV interposers and integrated passive devices offer an attractive opportunity for foundries to use their tools and processes to cross over into the packaging realm.  An assortment of business models is being considered, from full turn-key to various collaborative models.  This session will focus on the foundry perspective on these business models and strategies.  Panelists include:

  • Jerry Tzou, TSMC
  • David McCann, GLOBALFOUNDRIES
  • Kurt Huang, UMC
  • Regina Darmoni, IBM Corporation
  • Herb Huang, SMIC

From 2:00-4:00pm, the 2013 ECTC Modeling Session will tackle the complicated issue of 3D System design and processes, and the additional challenges 3D brings to current simulation methodologies and tools.  With discussions ranging from thermo-mechanical challenges for 3D system processes, critical design parameters of TSV stacking, to electrical simulation for signal and power integrity, electrical and thermal integrity optimization, and cloud-based scalable solutions for 3D system modeling, this special session will shed some light on how to address these challenges.

Imec’s Eric Beyne kicks off the thermo-mechanical portion with a keynote “Thermo-Mechanical Modeling of 3D Integration Technology: Impact of Actual Process Conditions and Non-ideal Material Properties on Modeling Results”, followed by related presentations by Kamal Karimanal, Cielution LLC, and a team from imec.

The second keynote of the session, “Cloud-Based Scalable Electromagnetic Solvers for 3D  Package Modeling,” presented by Vikram Jandhyala, of University of Washington, Nimbic, will be followed by Signal and Power Integrity Analysis of a 256GB/s Double-Sided IC Package with a Memory Controller and 3D Stacked DRAM, the work of team from Rambus. Lastly from Georgia Tech is Optimization of 3D Stack for Electrical and Thermal Integrity.

Incidentally, Kamal Karimanal will be doing double duty on Tuesday, offering a professional half-day development course Tuesday morning entitled Thermal and Mechanical Simulation Techniques for 3D Stacking Yield and Reliability.  If you found Karimanal’s presentation on this topic at IMAPS DPC interesting, you’ll want to put it on your list. I suspect given the time allotted there will be lots more detail than he could share then.

Tuesday afternoon choices for 3D-focused professional development courses include 3D IC Packaging and Integration, and 3D Si Integration, lead by John Lau, ITRI, which appears to be a soup-to-nuts look at the world of heterogeneous 3D integration, including MEMS and LEDs.

Option 2: Chip Package Interaction with TSV reliability for 40nm and Below lead C. S. Premachandran, GLOBALFOUNDRIES. This course will look at some of the next challenges facing 3D ICs as nodes become smaller and chip package interaction (CPI) becomes more critical.  If you work in the advanced packaging area <28nm nodes and want to understand the CPI, you won’t want to miss this.

Here’s a quick, by-number guide of sessions to choose from if you want to build a strictly 3D packaging and 3D IC focused itinerary:

  • Wednesday morning, choose from Session 1 (3D Assembly and Reliability), and Session 2 (3D Materials and Processing) (or alternate between the two). Additionally, Session 5, New Directions in Packaging offers a couple TSV focused presentations.
  •  Wednesday afternoon is a toss-up between Session 7 (Interposers) and 8, (3D Reliability and Packaging Challenges)
  • Thursday morning kicks off with Session 13 (3D Processing and Technology) and Session 14, (3D TSV Interconnects Reliability)
  • Thursday afternoon, the choice once again is between 2.5D and 3D ICs with Session 19 (Interposer Characterization) and Session 20 (Challenges in 3D Integration), with a few 3D topics thrown into Session 24 (Power and Signal Integrity) for good measure.
  • Friday morning drill down into nitty–gritty 3D topics in Sessions 25 (3D Microbump Structures and Silicon to Silicon Bonding) and 26 (High Speed interconnects & Power Distribution in 3D Integration)
  • Friday afternoon, there’s Session 31 (TSV Innovation and Implementation) and in Session 32 (Thermal and Mechanical Modeling: LED and 3D Structures) LEDS and 3D is lumped together.

To recap, while there’s a smattering of 3D focused presentations in other session tracks, to get the most 3D bang for your registration fee, stick to these sessions: 1, 2, 5, 7, 8, 13, 14, 19, 20, 24, 25, 26, 31, and 32. Find the full agenda and registration information here.

Francoise von Trapp

They call me the “Queen of 3D” because I have been following the course of…

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